ZHCSIA7 May   2018 DLPA4000

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      系统方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Parameters
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Description
    3. 7.3 Feature Description
      1. 7.3.1 Supply and Monitoring
        1. 7.3.1.1 Supply
        2. 7.3.1.2 Monitoring
          1. 7.3.1.2.1 Block Faults
          2. 7.3.1.2.2 Low Battery and UVLO
          3. 7.3.1.2.3 Thermal Protection
      2. 7.3.2 Illumination
        1. 7.3.2.1 Programmable Gain Block
        2. 7.3.2.2 LDO Illumination
        3. 7.3.2.3 Illumination Driver A
        4. 7.3.2.4 External MOSFETs
          1. 7.3.2.4.1 Gate series resistor (RG)
          2. 7.3.2.4.2 Gate series diode (DG)
          3. 7.3.2.4.3 Gate parallel capacitance (CG)
        5. 7.3.2.5 RGB Strobe Decoder
          1. 7.3.2.5.1 Break Before Make (BBM)
          2. 7.3.2.5.2 Openloop Voltage
          3. 7.3.2.5.3 Transient Current Limit
        6. 7.3.2.6 Illumination Monitoring
          1. 7.3.2.6.1 Power Good
          2. 7.3.2.6.2 RatioMetric Overvoltage Protection
      3. 7.3.3 External Power MOSFET Selection
        1. 7.3.3.1 Threshold Voltage
        2. 7.3.3.2 Gate Charge and Gate Timing
        3. 7.3.3.3 On-resistance RDS(on)
      4. 7.3.4 DMD Supplies
        1. 7.3.4.1 LDO DMD
        2. 7.3.4.2 DMD HV Regulator
        3. 7.3.4.3 DMD/DLPC Buck Converters
        4. 7.3.4.4 DMD Monitoring
          1. 7.3.4.4.1 Power Good
          2. 7.3.4.4.2 Overvoltage Fault
      5. 7.3.5 Buck Converters
        1. 7.3.5.1 LDO Bucks
        2. 7.3.5.2 General Purpose Buck Converters
        3. 7.3.5.3 Buck Converter Monitoring
          1. 7.3.5.3.1 Power Good
          2. 7.3.5.3.2 Overvoltage Fault
      6. 7.3.6 Auxiliary LDOs
      7. 7.3.7 Measurement System
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 Interrupt
      3. 7.5.3 Fast-Shutdown in Case of Fault
      4. 7.5.4 Protected Registers
      5. 7.5.5 Writing to EEPROM
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection for General-Purpose Buck Converters
    3. 8.3 System Example With DLPA4000 Internal Block Diagram
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up and Power-Down Timing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 LED Driver
        1. 10.1.1.1 PowerBlock Gate Control Isolation
        2. 10.1.1.2 VIN to PowerBlocks
        3. 10.1.1.3 Return Current from LEDs and RSense
        4. 10.1.1.4 RC Snubber
        5. 10.1.1.5 Capacitor Choice
      2. 10.1.2 General Purpose Buck 2
      3. 10.1.3 SPI Connections
      4. 10.1.4 RLIM Routing
      5. 10.1.5 LED Connection
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.1 Layout Guidelines

Make sure to consider high peak currents and high switching frequencies when designing the layout to avoid instability and EMI problems.

  • Use wide and short traces for high-current paths and for high-current return power ground paths.
  • Place, the input capacitor, output capacitor, and the inductor of the DMD HV regulator as close as possible to the DLPA4000 device.
  • Separate the ground traces and connect them together at a central point undermeath the device package. This design minimizes ground noise coupling between different buck converters
  • The recommended value for the DMD capacitors is 1 µF for VRST and VOFS, 470 nF for VBIAS. The inductor value is 10 µH.

The currents of the buck converters are highest near pins VIN, SWITCH and PGND (). The voltage at the pins VIN, PGND and FB are DC voltages. the SWITCH pin voltage a value betweent eh value of the VIN viltage and teh PGND voltage. The red line in Figure 25 indicates the current flow when the MOSFET between pin 52 and pin 53 is closed. The blue line indicates the current flow when the MOSFET between pin 53 and pin 54 is closed.

The buck converter paths carry the highest currents. Make sure the buck converter paths are as short as possible.

For the LDO DMD, it is recommended to use a 1-µF, 16-V capacitor on the input and a 10-µF, 6.3-V capacitor on the output of the LDO assuming a battery voltage of 12 V.

For LDO bucks, it is recommended to use a 1-µF, 16-V capacitor on the input and a 1-µF, 6.3-V capacitor on the output of the LDO.

DLPA4000 High_Current_Paths.gifFigure 25. High AC Current Paths in a Buck Converter

The trace to the VIN pin in this design has high AC currents that prevents voltage drop across the trace. Make sure the trace to the VIN pin has low resistance.

Place the decoupling capacitors as close to the VIN pin as possible.

The SWITCH pin alternates connection to the VIN pin or GND. The SWITCH pin voltage waveform is square with an amplitude equal to VIN. The SWITCH pin voltage containing high frequencies. This situation causes EMI problems unless properly mitigated. Reduce EMI by creating a snubber network (RSN7 and CSN7) Place the resistor and capacitor at the SWITCH pin to prevent or suppress unwanted high-frequency ringing during switching.

The PGND pin sinks high current. Connect the PGND pin to a star ground point so that it does not interfere with other ground connections.

The FB pin is the sense connection for the regulated DC output voltage. No current flows through the FB pin. The device compares the voltage on the FB pin with the internal reference voltage. This comparison controls the loop. Make the FB connection at the load so that the I-R drop does not affect the sensed voltage.