ZHCSCO5B June 2014 – February 2018 DLPA2000
PRODUCTION DATA.
REGISTER | ADDRESS (HEX) | NAME | TABLE | DESCRIPTION | DEFAULT |
---|---|---|---|---|---|
USER CONFIGURATION DEFINITIONS | |||||
R | 0x00 | CHIP ID | Figure 15 | Chip revision register; DLPA2000 | B3 |
R/W | 0x01 | CHIPENABLE | Figure 16 | Enable register | 0F |
R/W | 0x02 | IREG | Figure 17 | Transient-current limit settings | 30 |
R/W | 0x03 | SW4MSB | Figure 18 | Regulation current MSB, SW4 | 0 |
R/W | 0x04 | SW4LSB | Table 12, Table 13 | Regulation current LSB, SW4 | 0 |
R/W | 0x05 | SW5MSB | Figure 20 | Regulation current MSB, SW5 | 0 |
R/W | 0x06 | SW5LSB | Figure 21, Table 16 | Regulation current LSB, SW5 | 0 |
R/W | 0x07 | SW6MSB | Figure 22 | Regulation current MSB, SW6 | 0 |
R/W | 0x08 | SW6LSB | Figure 23, Table 19 | Regulation current LSB, SW6 | 0 |
R/W | 0x09 | SWCNTRL | Figure 24 | Switch ON/OFF control (direct mode) | 0 |
R/W | 0x0A | AFE | Figure 25 | AFE (MUX) control | 0 |
R/W | 0x0B | BBM | Figure 26, Table 22 | Break before make timing | 0 |
R | 0x0C | INT | Figure 27, Table 23 | Interrupt register | 0 |
R/W | 0x0D | INT MASK | Figure 28, Table 24 | Interrupt mask register | DFh |
R/W | 0x0E | TIMING | Figure 29, Table 26 | Timing register VOFS, VBIAS, VRST, and RESETZ | 7 |
R/W | 0x0F | MOTOR CTRL | Figure 30, Table 27 | Motor control register | 0 |
USER PROTECTED DEFINITION | |||||
R/W | 0x10 | PASSWORD | Figure 31 | Password register | 0 |
R/W | 0x11 | SYSTEM | Figure 32 | System configuration register | 0 |
USER EEPROM SCRATCH PAD DEFINITION | |||||
R/W | 0x20 | BYTE0 | Figure 33 | User EEPROM, Byte0 | 0 |
R/W | 0x21 | BYTE1 | Figure 34 | User EEPROM, Byte1 | 0 |
R/W | 0x22 | BYTE2 | Figure 35 | User EEPROM, Byte2 | 0 |
R/W | 0x23 | BYTE3 | Figure 36 | User EEPROM, Byte3 | 0 |
R/W | 0x24 | BYTE4 | Figure 37 | User EEPROM, Byte4 | 0 |
R/W | 0x25 | BYTE5 | Figure 38 | User EEPROM, Byte5 | 0 |
R/W | 0x26 | BYTE6 | Figure 39 | User EEPROM, Byte6 | 0 |
R/W | 0x27 | BYTE7 | Figure 40 | User EEPROM, Byte7 | 0 |