ZHCSM38 december   2020 DAC43701 , DAC53701

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Standard Mode
    7. 7.7  Timing Requirements: I2C Fast Mode
    8. 7.8  Timing Requirements: I2C Fast Mode Plus
    9. 7.9  Timing Requirements: GPI
    10. 7.10 Timing Diagram
    11. 7.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 7.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 7.13 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 Reference Selection and DAC Transfer Function
          1. 8.3.1.1.1 Power Supply as Reference
          2. 8.3.1.1.2 Internal Reference
      2. 8.3.2 General-Purpose Input (GPI)
      3. 8.3.3 DAC Update
        1. 8.3.3.1 DAC Update Busy
      4. 8.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 8.3.4.1 NVM Cyclic Redundancy Check
        2. 8.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 8.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 8.3.5 Programmable Slew Rate
      6. 8.3.6 Power-on-Reset (POR)
      7. 8.3.7 Software Reset
      8. 8.3.8 Device Lock Feature
      9. 8.3.9 PMBus Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down Mode
      2. 8.4.2 Continuous Waveform Generation (CWG) Mode
      3. 8.4.3 PMBus Compatibility Mode
      4. 8.4.4 Medical Alarm Generation Mode
        1. 8.4.4.1 Low-Priority Alarm
        2. 8.4.4.2 Medium-Priority Alarm
        3. 8.4.4.3 High-Priority Alarm
        4. 8.4.4.4 Interburst Time
        5. 8.4.4.5 Pulse Off Time
        6. 8.4.4.6 Pulse On Time
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 I2C Update Sequence
        1. 8.5.2.1 Address Byte
          1. 8.5.2.1.1 Slave Address Configuration
        2. 8.5.2.2 Command Byte
      3. 8.5.3 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 8.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 8.6.3  CONFIG2 Register (address = D2h) [reset = 0000h]
      4. 8.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 8.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 8.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
      7. 8.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
      8. 8.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 8.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 8.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Appliance Light Fade-In Fade-Out
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Power-Supply Margining
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Medical Alarm Generation
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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8.3.5 Programmable Slew Rate

When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new code following the slew rate and settling time specified in Section 7.5. The slew rate control feature allows the user to control the rate at which the output voltage (VOUT) changes. When this feature is enabled (using SLEW_RATE[3:0] bits), the DAC output changes from the current code to the code in MARGIN_HIGH (address 25h) or MARGIN_LOW (address 26h) registers (when margin high or low commands are issued to the DAC) using the step and rate set in CODE_STEP and SLEW_RATE bits. With the default slew rate control setting (CODE_STEP and SLEW_RATE bits, address D1h), the output changes smoothly at a rate limited by the output drive circuitry and the attached load. Using this feature, the output steps digitally at a rate defined by bits CODE_STEP and SLEW_RATE on address D1h. SLEW_RATE defines the rate at which the digital slew updates; CODE_STEP defines the amount by which the output value changes at each update. Table 8-3 and Table 8-4 show different settings for CODE_STEP and SLEW_RATE.

When the slew rate control feature is used, the output changes happen at the programmed slew rate. This configuration results in a staircase formation at the output. Do not write to CODE_STEP, SLEW_RATE, or DAC_DATA during the output slew.

Table 8-3 Code Step
REGISTER ADDRESS AND NAME CODE_STEP[2] CODE_STEP[1] CODE_STEP[0] COMMENT
D1h, GENERAL_CONFIG 0 0 0 Code step size = 1 LSB (default)
0 0 1 Code step size = 2 LSB
0 1 0 Code step size = 3 LSB
0 1 1 Code step size = 4 LSB
1 0 0 Code step size = 6 LSB
1 0 1 Code step size = 8 LSB
1 1 0 Code step size = 16 LSB
1 1 1 Code step size = 32 LSB
Table 8-4 Slew Rate
REGISTER ADDRESS AND NAMESLEW_RATE[3]SLEW_RATE[2]SLEW_RATE[1]SLEW_RATE[0]TIME PERIOD (PER STEP)
D1h, GENERAL_CONFIG000025.6 µs
000132 µs
001038.4 µs
001144.8 µs
0100204.8 µs
0101256 µs
0110307.2 µs
0111819.2 µs
10001638.4 µs
10012457.6 µs
10103276.8 µs
10114915.2 µs
110012 µs
11018 µs
11104 µs
11110 µs, no slew (default)