ZHCSBF0D August 2013 – February 2018 DAC3151 , DAC3161 , DAC3171
PRODUCTION DATA.
Register Name | Addr (Hex) | Bit | Name | Function | Default Value |
---|---|---|---|---|---|
config3 | 0x03 | 15:13 | datadlya | Controls the delay of the D[13:7]P/N inputs through the LVDS receivers for single bus mode; controls the delay of the DA[6:0]P/N inputs through the LVDS receivers for dual bus mode (only applicable to DAC3171). 0= no additional delay and each LSB adds a nominal 80ps. | 000 |
12:10 | clkdlya | Controls the delay of the SYNCP/N inputs through the LVDS receivers for single bus mode; controls the delay of the DA_CLKP/N inputs through the LVDS receivers for dual bus mode (only applicable to DAC3171). 0= no additional delay and each LSB adds a nominal 80ps. | 000 | ||
9:7 | datadlyb | Controls the delay of the D[6:0]P/N inputs through the LVDS receivers for single bus mode; controls the delay of the DB[6:0]P/N inputs through the LVDS receivers for dual bus mode (only applicable to DAC3171). | 000 | ||
6:4 | clkdlyb | Controls the delay of the DATACLKP/N inputs through the LVDS receivers for single bus mode; controls the delay of the DB_CLKP/N inputs through the LVDS receivers for dual bus mode (only applicable to DAC3171). 0= no additional delay and each LSB adds a nominal 80ps. | 000 | ||
3 | extref_ ena | Enable external reference for the DAC when set. | 0 | ||
2:1 | reserved | reserved | 00 | ||
0 | dual_ena | When this bit is set, pins 6,7 become the DATACLK for the data into the FIFO while in 7-bit DDR mode for DAC3171. When this bit is not set, pins 24,25 become the DATACLK for the data into the FIFO. While in full-word interface mode, leave this bit at 0. | 0 |