ZHCSAO1D January   2013  – August 2016 CSD97374Q4M

 

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Powering CSD97374Q4M and Gate Drivers
    3. 7.3 Undervoltage Lockout Protection (UVLO)
    4. 7.4 PWM Pin
    5. 7.5 SKIP# Pin
      1. 7.5.1 Zero Crossing (ZX) Operation
    6. 7.6 Integrated Boost-Switch
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Loss Curves
    3. 8.3 Safe Operating Curves (SOA)
    4. 8.4 Normalized Curves
    5. 8.5 Calculating Power Loss and SOA
      1. 8.5.1 Design Example
      2. 8.5.2 Calculating Power Loss
      3. 8.5.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
      3. 9.1.3 Thermal Performance
    2. 9.2 Layout Example
  10. 10器件和文档支持
    1. 10.1 接收文档更新通知
    2. 10.2 社区资源
    3. 10.3 商标
    4. 10.4 静电放电警告
    5. 10.5 Glossary
  11. 11机械封装和可订购信息
    1. 11.1 机械尺寸
    2. 11.2 推荐 PCB 焊盘图案
    3. 11.3 建议模板开口

封装选项

机械数据 (封装 | 引脚)
  • DPC|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.2 Power Loss Curves

MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD97374Q4M as a function of load current. This curve is measured by configuring and running the CSD97374Q4M as it would be in the final application (see Figure 14). The measured power loss is the CSD97374Q4M device power loss which consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Equation 1. Power loss = (VIN× IIN) + (VDD × IDD) – (VSW_AVG × IOUT)

The power loss curve in Figure 1 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.