ZHCS385D June   2013  – February 2024 CDCE913-Q1 , CDCEL913-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Configuration
      2. 8.3.2 Default Device Configuration
      3. 8.3.3 I2C Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Hardware Interface
    5. 8.5 Programming
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread-Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Register Maps
    1. 10.1 I2C Configuration Registers
  12. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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6.3 Recommended Operating Conditions

MINNOMMAXUNIT
VDDDevice supply voltage1.71.81.9V
VOOutput Yx supply voltage, VDDOUTCDCE913-Q12.33.6V
CDCEL913-Q11.71.9
VILLow-level input voltage, LVCMOS0.3 × VDDV
VIHHigh-level input voltage, LVCMOS0.7 × VDDV
VI(thresh)Input voltage threshold, LVCMOS0.5 × VDDV
VI(S)Input voltageS001.9V
S1, S2, SDA, SCL (VI(thresh) = 0.5 VDD)03.6
VI(CLK)Input voltage range CLK01.9V
IOH, IOLOutput currentVDDOUT = 3.3 V±12mA
VDDOUT = 2.5 V±10
VDDOUT = 1.8 V±8
CLOutput load, LVCMOS15pF
TAOperating ambient temperatureCDCE913-Q1–40125°C
CDCEL913-Q1–4085
CRYSTAL AND VCXO SPECIFICATIONS(1)
fXtalCrystal input frequency (fundamental mode)82732MHz
ESREffective series resistance100Ω
fPRPulling range (0 V ≤ Vctr ≤ 1.8 V)(2)±120±150ppm
VctrFrequency control voltage0VDDV
C0 / C1Pullability ratio220
CLOn-chip load capacitance at Xin and Xout020pF
(1) For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
(2) Pulling range depends on crystal type, on-chip crystal load capacitance, and PCB stray capacitance; pulling range of minimum ±120 ppm applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).