ZHCS385D June   2013  – February 2024 CDCE913-Q1 , CDCEL913-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Configuration
      2. 8.3.2 Default Device Configuration
      3. 8.3.3 I2C Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Hardware Interface
    5. 8.5 Programming
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread-Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Register Maps
    1. 10.1 I2C Configuration Registers
  12. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSMINTYP(1)MAXUNIT
OVERALL PARAMETER
IDDSupply current (see Figure 6-1)All outputs off,
fCLK = 27 MHz,
fVCO = 135 MHz,
fOUT = 27 MHz		All PLLS on11mA
Per PLL9
IDD(OUT)Supply current (see Figure 6-2 and Figure 6-3)No load, all outputs on,
fOUT = 27 MHz		VDDOUT = 3.3 V1.3mA
VDDOUT = 1.8 V0.7
IDD(PD)Power-down current. Every circuit powered down except I2CfIN = 0 MHz, VDD = 1.9 V30µA
V(PUC)Supply voltage VDD threshold for power-up control circuit0.851.45V
fVCOVCO frequency range of PLL80230MHz
fOUTLVCMOS output frequencyVDDOUT = 3.3 V230MHz
VDDOUT = 1.8 V230
LVCMOS PARAMETER
VIKLVCMOS input voltageVDD = 1.7 V, II = –18 mA–1.2V
IILVCMOS input currentVI = 0 V or VDD, VDD = 1.9 V±5µA
IIHLVCMOS input current for S0, S1, and S2VI = VDD, VDD = 1.9 V5µA
IILLVCMOS input current for S0, S1, and S2VI = 0 V, VDD = 1.9 V–4µA
CIInput capacitance at Xin/CLKVIClk = 0 V or VDD6pF
Input capacitance at XoutVIXout = 0 V or VDD2
Input capacitance at S0, S1, and S2VIS = 0 V or VDD3
CDCE913-Q1, LVCMOS PARAMETER FOR VDDOUT = 3.3-V MODE
VOHLVCMOS high-level output voltageVDDOUT = 3 V, IOH = –0.1 mA2.9V
VDDOUT = 3 V, IOH = –8 mA2.4
VDDOUT = 3 V, IOH = –12 mA2.2
VOLLVCMOS low-level output voltageVDDOUT = 3 V, IOL = 0.1 mA0.1V
VDDOUT = 3 V, IOL = 8 mA0.5
VDDOUT = 3 V, IOL = 12 mA0.8
tPLH, tPHLPropagation delayPLL bypass3.2ns
tr, tfRise and fall timeVDDOUT = 3.3 V (20%–80%)0.6ns
tjit(cc)Cycle-to-cycle jitter for Y1 to Y3(2)(3)1 PLL switching, Y2-to-Y3, 10,000 cycles50200ps
tjit(per)Peak-to-peak period jitter for Y1 to Y3(2)(3)1 PLL switching, Y2-to-Y360200ps
tsk(o)Output skew (see Table 8-2)(4)fOUT = 50 MHz, Y1-to-Y3440ps
odcOutput duty cycle (5)fVCO = 100 MHz, Pdiv = 145%55%
CDCE913-Q1, LVCMOS PARAMETER FOR VDDOUT = 2.5-V MODE
VOHLVCMOS high-level output voltageVDDOUT = 2.3 V, IOH = –0.1 mA2.2V
VDDOUT = 2.3 V, IOH = –6 mA1.7
VDDOUT = 2.3 V, IOH = –10 mA1.6
VOLLVCMOS low-level output voltageVDDOUT = 2.3 V, IOL = 0.1 mA0.1V
VDDOUT = 2.3 V, IOL = 6 mA0.5
VDDOUT = 2.3 V, IOL = 10 mA0.7
tPLH, tPHLPropagation delayPLL bypass3.6ns
tr, tfRise and fall timeVDDOUT = 2.5 V (20%–80%)0.8ns
tjit(cc)Cycle-to-cycle jitter for Y1 to Y3(2)(3)1 PLL switching, Y2-to-Y3, 10,000 cycles50200ps
tjit(per)Peak-to-peak period jitter for Y1 to Y3(2)(3)1 PLL switching, Y2-to-Y360200ps
tsk(o)Output skew (see Table 8-2)(4)fOUT = 50 MHz, Y1-to-Y3440ps
odcOutput duty cycle(5)fVCO = 100 MHz, Pdiv = 145%55%
CDCEL913-Q1, LVCMOS PARAMETER FOR VDDOUT = 1.8-V MODE
VOHLVCMOS high-level output voltageVDDOUT = 1.7 V, IOH = –0.1 mA1.6V
VDDOUT = 1.7 V, IOH = –4 mA1.4
VDDOUT = 1.7 V, IOH = –8 mA1.1
VOLLVCMOS low-level output voltageVDDOUT = 1.7 V, IOL = 0.1 mA0.1V
VDDOUT = 1.7 V, IOL = 4 mA0.3
VDDOUT = 1.7 V, IOL = 8 mA0.6
tPLH, tPHLPropagation delayPLL bypass2.6ns
tr, tfRise and fall timeVDDOUT = 1.8 V (20%–80%)0.7ns
tjit(cc)Cycle-to-cycle jitter for Y1 to Y3(2)(3)1 PLL switching, Y2-to-Y3, 10,000 cycles80110ps
tjit(per)Peak-to-peak period jitter for Y1 to Y3(2)(3)1 PLL switching, Y2-to-Y3100130ps
tsk(o)Output skew (see Table 8-2)(4)fOUT = 50 MHz, Y1-to-Y350ps
odcOutput duty cycle(5)fVCO = 100 MHz, Pdiv = 145%55%
I2C PARAMETER
VIKSCL and SDA input clamp voltageVDD = 1.7 V, II = –18 mA–1.2V
IIHSCL and SDA input currentVI = VDD, VDD = 1.9 V±10µA
VIHI2C input high voltage(6)0.7 × VDDV
VILI2C input low voltage(6)0.3 × VDDV
VOLSDA low-level output voltageIOL = 3 mA, VDD = 1.7 V0.2 × VDDV
CISCL-SDA input capacitanceVI = 0 V or VDD310pF
EEPROM SPECIFICATION
EEcycProgramming cycles of EEPROM1001000cycles
EEretData retention10years
(1) All typical values are at respective nominal VDD.
(2) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).
(3) Y1 supplied by PLL1 and configured to same frequency as Y2.
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.
(5) odc depends on the output rise and fall time (tr and tf); data sampled on the rising edge (tr)
(6) SDA and SCL pins are 3.3-V tolerant.