ZHCSQO2L august   1998  – september 2023 CD4051B , CD4052B , CD4053B

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

GUID-D92016BA-5EE2-41AC-9ACB-FC6AD141AF1C-low.gifFigure 5-1 CD4051B E, M, NS, and PW Package,16-Pin PDIP, CDIP, SOIC, SOP, and TSSOP(Top View)
GUID-2CA2AAAC-9EA6-4603-B325-CEDEA3EC5BBB-low.gifFigure 5-2 CD4052B E, M, NS, and PW Package,16-Pin PDIP, CDIP, SOP, and TSSOP(Top View)
GUID-4D77DFE3-7CFF-4BAA-BD57-E9858FA788F8-low.gifFigure 5-3 CD4053B E, M, NS, and PW Package,16-Pin PDIP, CDIP, SOP, and TSSOP (Top View)
Table 5-1 Pin Functions CD4051B
PIN TYPE(1) DESCRIPTION
NO. NAME
1 CH 4 IN/OUT I/O Channel 4 in/out
2 CH 6 IN/OUT I/O Channel 6 in/out
3 COM OUT/IN I/O Common out/in
4 CH 7 IN/OUT I/O Channel 7 in/out
5 CH 5 IN/OUT I/O Channel 5 in/out
6 INH I Disables all channels. See Table 8-1.
7 VEE — Negative power input
8 VSS — Ground
9 C I Channel select C. See Table 8-1.
10 B I Channel select B. See Table 8-1.
11 A I Channel select A. See Table 8-1.
12 CH 3 IN/OUT I/O Channel 3 in/out
13 CH 0 IN/OUT I/O Channel 0 in/out
14 CH 1 IN/OUT I/O Channel 1 in/out
15 CH 2 IN/OUT I/O Channel 2 in/out
16 VDD — Positive power input
(1) I = input, O = output
Table 5-2 Pin Functions CD4052B
PIN TYPE(1) DESCRIPTION
NO. NAME
1 Y CH 0 IN/OUT I/O Channel Y0 in/out
2 Y CH 2 IN/OUT I/O Channel Y2 in/out
3 Y COM OUT/IN I/O Y common out/in
4 Y CH 3 IN/OUT I/O Channel Y3 in/out
5 Y CH 1 IN/OUT I/O Channel Y1 in/out
6 INH I Disables all channels. See Table 8-1.
7 VEE — Negative power input
8 VSS — Ground
9 B I Channel select B. See Table 8-1.
10 A I Channel select A. See Table 8-1.
11 X CH 3 IN/OUT I/O Channel X3 in/out
12 X CH 0 IN/OUT I/O Channel X0 in/out
13 X COM IN/OUT I/O X common out/in
14 X CH 1 IN/OUT I/O Channel in/out
15 X CH 2 IN/OUT I/O Channel in/out
16 VDD — Positive power input
(1) I = input, O = output
Table 5-3 Pin Functions CD4053B
PIN TYPE(1) DESCRIPTION
NO. NAME
1 BY IN/OUT I/O B channel Y in/out
2 BX IN/OUT I/O B channel X in/out
3 CY IN/OUT I/O C channel Y in/out
4 CX OR CY OUT/IN I/O C common out/in
5 CX IN/OUT I/O C channel X in/out
6 INH I Disables all channels. See Table 8-1.
7 VEE — Negative power input
8 VSS — Ground
9 C I Channel select C. See Table 8-1.
10 B I Channel select B. See Table 8-1.
11 A I Channel select A. See Table 8-1.
12 AX IN/OUT I/O A channel X in/out
13 AY IN/OUT I/O A channel Y in/out
14 AX OR AY OUT/IN I/O A common out/in
15 BX OR BY OUT/IN I/O B common out/in
16 VDD — Positive power input
(1) I = input, O = output