ZHCSFX3A April   2016  – November 2016 CC2564C

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 VQFN-MR Pin Diagram
      1. 4.1.1 Pin Attributes (VQFN-MR Package)
      2. 4.1.2 Connections for Unused Signals (VQFN-MR Package)
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. 5.5.1 Static Current Consumption
      2. 5.5.2 Dynamic Current Consumption
        1. 5.5.2.1 Current Consumption for Different Bluetooth BR and EDR Scenarios
        2. 5.5.2.2 Current Consumption for Different Low-Energy Scenarios
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics for VQFN-MR (RVM) Package
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1 Device Power Supply
        1. 5.8.1.1 Power Sources
        2. 5.8.1.2 Device Power-Up and Power-Down Sequencing
        3. 5.8.1.3 Power Supplies and Shutdown—Static States
        4. 5.8.1.4 I/O States in Various Power Modes
        5. 5.8.1.5 nSHUTD Requirements
      2. 5.8.2 Clock Specifications
        1. 5.8.2.1 Slow Clock Requirements
        2. 5.8.2.2 External Fast Clock Crystal Requirements and Operation
        3. 5.8.2.3 Fast Clock Source Requirements (-40°C to +85°C)
      3. 5.8.3 Peripherals
        1. 5.8.3.1 UART
        2. 5.8.3.2 PCM
      4. 5.8.4 RF Performance
        1. 5.8.4.1 Bluetooth BR and EDR RF Performance
          1. 5.8.4.1.1 Bluetooth Receiver—In-Band Signals
          2. 5.8.4.1.2 Bluetooth Receiver—General Blocking
          3. 5.8.4.1.3 Bluetooth Transmitter—GFSK
          4. 5.8.4.1.4 Bluetooth Transmitter—EDR
          5. 5.8.4.1.5 Bluetooth Modulation—GFSK
          6. 5.8.4.1.6 Bluetooth Modulation—EDR
          7. 5.8.4.1.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions
        2. 5.8.4.2 Bluetooth low energy RF Performance
          1. 5.8.4.2.1 Bluetooth low energy Receiver—In-Band Signals
          2. 5.8.4.2.2 Bluetooth low energy Receiver—General Blocking
          3. 5.8.4.2.3 Bluetooth low energy Transmitter
          4. 5.8.4.2.4 Bluetooth low energy Modulation
          5. 5.8.4.2.5 Bluetooth low energy Transceiver, Out-Of-Band and Spurious Emissions
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Clock Inputs
      1. 6.3.1 Slow Clock
      2. 6.3.2 Fast Clock Using External Clock Source
        1. 6.3.2.1 External FREF DC-Coupled
        2. 6.3.2.2 External FREF Sine Wave, AC-Coupled
        3. 6.3.2.3 Fast Clock Using External Crystal
    4. 6.4 Functional Blocks
      1. 6.4.1 RF
        1. 6.4.1.1 Receiver
        2. 6.4.1.2 Transmitter
      2. 6.4.2 Host Controller Interface
        1. 6.4.2.1 4-Wire UART Interface—H4 Protocol
        2. 6.4.2.2 3-Wire UART Interface—H5 Protocol
      3. 6.4.3 Digital Codec Interface
        1. 6.4.3.1 Hardware Interface
        2. 6.4.3.2 I2S
        3. 6.4.3.3 Data Format
        4. 6.4.3.4 Frame-Idle Period
        5. 6.4.3.5 Clock-Edge Operation
        6. 6.4.3.6 Two-Channel Bus Example
      4. 6.4.4 Assisted Modes
        1. 6.4.4.1 Assisted HFP 1.6 (WBS)
        2. 6.4.4.2 Assisted A2DP
          1. 6.4.4.2.1 Assisted A2DP Sink
          2. 6.4.4.2.2 Assisted A2DP Source
    5. 6.5 Bluetooth BR and EDR Features
    6. 6.6 Bluetooth low energy Description
    7. 6.7 Bluetooth Transport Layers
    8. 6.8 Changes from the CC2564B Device to the CC2564C Device
  7. 7Applications, Implementation, and Layout
    1. 7.1 Reference Design Schematics and BOM for Power and Radio Connections
    2. 7.2 PCB Layout Guidelines
      1. 7.2.1 General PCB Guidelines
      2. 7.2.2 Power Supply Guidelines
      3. 7.2.3 User Interfaces
      4. 7.2.4 Clock Interfaces
      5. 7.2.5 RF Interface
  8. 8器件和文档支持
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 工具与软件
    3. 8.3 器件命名规则
    4. 8.4 Community Resources
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 Glossary
  9. 9机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RVM|76
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Specifications

Unless otherwise indicated, all measurements are taken at the device pins of the TI test evaluation board (EVB). All specifications are over process, voltage, and temperature, unless otherwise indicated.

5.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise indicated). All parameters are measured as follows:
VDD_IN = 3.6 V and VDD_IO = 1.8 V (unless otherwise indicated).
MIN MAX UNIT
Supply voltage VDD_IN –0.5 4.8 V(2)
VDDIO_1.8 V –0.5 2.145 V
Input voltage to analog pins(3) –0.5 2.1 V
Input voltage to all other pins –0.5 VDD_IO + 0.5 V
Bluetooth RF inputs 10 dBm
Operating ambient temperature, TA(4) –40 85 °C
Storage temperature, Tstg –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 7.1.
(3) Analog pins: BT_RF, XTALP, and XTALM
(4) The reference design supports a temperature range of –20°C to +70°C because of the operating conditions of the crystal.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±500 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Power-On Hours

DEVICE CONDITIONS POWER-ON HOURS
CC2564C Duty cycle = 25% active and 75% sleep
Tambient = 85ºC		 15,400 (7 years)

5.4 Recommended Operating Conditions

MIN MAX UNIT
VDD_IN Power supply voltage 1.7 4.8 V
VDD_IO I/O power supply voltage 1.62 1.92 V
VIH High-level input voltage Default condition 0.65 × VDD_IO VDD_IO V
VIL Low-level input voltage Default condition 0 0.35 × VDD_IO V
tr and tf I/O input rise and all times,
10% to 90%—asynchronous mode		 1 10 ns
I/O input rise and fall times,
10% to 90%—synchronous mode (PCM)		 1 2.5 ns
Maximum ripple on VDD_IN (sine wave) for
1.8 V (DC-DC) mode		 Condition: 0 to 0.1 MHz 60 mVp-p
Condition: 0.1 to 0.5 MHz 50
Condition: 0.5 to 2.5 MHz 30
Condition: 2.5 to 3.0 MHz 15
Condition: > 3.0 MHz 5
Voltage dips on VDD_IN (VBAT)
Duration = 577 µs to 2.31 ms, period = 4.6 ms		 400 mV
Maximum ambient operating temperature(1) (2) –40 85 °C
(1) The device can be reliably operated for 7 years at Tambient of 85°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours).
(2) A crystal-based solution is limited by the temperature range required for the crystal to meet 20 ppm.

5.5 Power Consumption Summary

5.5.1 Static Current Consumption

OPERATIONAL MODE MIN TYP MAX UNIT
Shutdown mode(1) 1 7 µA
Deep sleep mode(2) 40 105 µA
Total I/O current consumption in active mode 1 mA
Continuous transmission—GFSK(3) 107 mA
Continuous transmission—EDR(4)(5) 112.5 mA
(1) VBAT + VIO + VSHUTDOWN
(2) VBAT + VIO
(3) At maximum output power dBm
(4) At maximum output power dBm
(5) Both π/4 DQPSK and 8DPSK

5.5.2 Dynamic Current Consumption

5.5.2.1 Current Consumption for Different Bluetooth BR and EDR Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz XTAL, nominal unit, 10-dBm output power
OPERATIONAL MODE MASTER AND SLAVE AVERAGE CURRENT UNIT
SCO link HV3 Master and slave 13.7 mA
Extended SCO (eSCO) link EV3 64 kbps, no retransmission Master and slave 13.2 mA
eSCO link 2-EV3 64 kbps, no retransmission Master and slave 10 mA
GFSK full throughput: TX = DH1, RX = DH5 Master and slave 40.5 mA
EDR full throughput: TX = 2-DH1, RX = 2-DH5 Master and slave 41.2 mA
EDR full throughput: TX = 3-DH1, RX = 3-DH5 Master and slave 41.2 mA
Sniff, four attempts, 1.28 seconds Master and slave 145 µA
Page or inquiry scan 1.28 seconds, 11.25 ms Master and slave 320 µA
Page (1.28 seconds) and inquiry (2.56 seconds) scans, 11.25 ms Master and slave 445 µA
A2DP source Master 13.9 mA
A2DP sink Master 15.2 mA
Assisted A2DP source Master 16.9 mA
Assisted A2DP sink Master 18.1 mA
Assisted WBS EV3; retransmit effort = 2;
maximum latency = 8 ms		 Master and slave 17.5 and 18.5 mA
Assisted WBS 2EV3; retransmit effort = 2;
maximum latency = 12 ms		 Master and slave 11.9 and 13 mA

5.5.2.2 Current Consumption for Different Low-Energy Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, nominal unit, 10-dBm output power
MODE DESCRIPTION AVERAGE CURRENT UNIT
Advertising, nonconnectable Advertising in all three channels
1.28-seconds advertising interval
15 bytes advertise data 		114 µA
Advertising, discoverable Advertising in all three channels
1.28-seconds advertising interval
15 bytes advertise data 		138 µA
Scanning Listening to a single frequency per window
1.28-seconds scan interval
11.25-ms scan window 		324 µA
Connected Master role 500-ms connection interval
0-ms slave connection latency
Empty TX and RX LL packets		 169 µA
Slave role 199

5.6 Electrical Characteristics

RATING CONDITION MIN MAX UNIT
High-level output voltage, VOH At 2, 4, 8 mA 0.8 × VDD_IO VDD_IO V
At 0.1 mA VDD_IO – 0.2 VDD_IO
Low-level output voltage, VOL At 2, 4, 8 mA 0 0.2 × VDD_IO V
At 0.1 mA 0 0.2
I/O input impedance Resistance 1 MΩ
Capacitance 5 pF
Output rise and fall times, 10% to 90% (digital pins) CL = 20 pF 10 ns
I/O pull currents PCM–I2S bus, TX_DBG PU Typical = 6.5 3.5 9.7 µA
PD Typical = 27 9.5 55
All others PU Typical = 100 50 300
PD Typical = 100 50 360

5.7 Thermal Resistance Characteristics for VQFN-MR (RVM) Package

over operating free-air temperature range (unless otherwise noted)
THERMAL METRICS(1) C/W(2)
Rθja Junction-to-free-air 34.6
Rθjctop Junction-to-case-top 17.9
Rθjcbottom Junction-to-case-bottom 1.6
Rθjb Junction-to-board 12.0
φjt Junction-to-package-top 0.2
φjb Junction-to-package-bottom 12.0
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
  • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
  • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

    • Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.

5.8 Timing and Switching Characteristics

5.8.1 Device Power Supply

The CC2564C power-management hardware and software algorithms provide significant power savings, which is a critical parameter in an MCU-based system.

The power-management module is optimized for drawing extremely low currents.

5.8.1.1 Power Sources

The CC2564C device requires two power sources:

  • VDD_IN: main power supply for the device
  • VDD_IO: power source for the 1.8-V I/O ring

The HCI module includes several on-chip voltage regulators for increased noise immunity and can be connected directly to the battery.

5.8.1.2 Device Power-Up and Power-Down Sequencing

The device includes the following power-up requirements (see Figure 5-1):

  • nSHUTD must be low. VDD_IN and VDD_IO are don't care I/O pins when nSHUTD is low. However, signals are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe. Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages with no VDD_IO and VDD_IN.
  • VDD_IO and VDD_IN must be stable before releasing nSHUTD.
  • The fast clock must be stable within 20 ms of nSHUTD going high.
  • The slow clock must be stable within 2 ms of nSHUTD going high.

The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to 100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case, ensure that the sequence and requirements are met.

CC2564C Power-up-power-down-sequencing-cc2564c.gif Figure 5-1 Power-Up and Power-Down Sequencing

5.8.1.3 Power Supplies and Shutdown—Static States

The nSHUTD signal puts the device in ultra-low-power mode and performs an internal reset to the device. The rise time for nSHUTD must not exceed 20 µs; nSHUTD must be low for a minimum of 5 ms.

To prevent conflicts with external signals, all I/O pins are set to the high-impedance (Hi-Z) state during shutdown and power up of the device. The internal pull resistors are enabled on each I/O pin, as described in Section 4.1.1. Table 5-1 lists and describes the static operation states.

Table 5-1 Power Modes

VDD_IN (1) VDD_IO(1) nSHUTD(1) PM_MODE COMMENTS
1 None None Asserted Shutdown I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins.
2 None None Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins.
3 None Present Asserted Shutdown I/Os are defined as tri-state pins with internal pullup or pulldown enabled.
4 None Present Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins.
5 Present None Asserted Shutdown I/O state is undefined.
6 Present None Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins.
7 Present Present Asserted Shutdown I/Os are defined as tri-state pins with internal pullup or pulldown enabled.
8 Present Present Deasserted Active See Section 5.8.1.4.
(1) The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through a pulldown resistor, or left NC or floating (high-impedance output stage).

5.8.1.4 I/O States in Various Power Modes

CAUTION

Some device I/Os are not fail-safe (see Section 4.1.1). Fail-safe means that the pins do not draw current from an external voltage applied to the pin when I/O power is not supplied to the device. External voltages are not allowed on these I/O pins when the I/O supply voltage is not supplied because of possible damage to the device.

Table 5-2 lists the I/O states in various power modes.

Table 5-2 I/O States in Various Power Modes

I/O NAME SHUTDOWN(1) DEFAULT ACTIVE(1) DEEP SLEEP(1)
I/O State Pull I/O State Pull I/O State Pull
HCI_RX Z PU I PU I PU
HCI_TX Z PU O-H O
HCI_RTS Z PU O-H O
HCI_CTS Z PU I PU I PU
AUD_CLK Z PD I PD I PD
AUD_FSYNC Z PD I PD I PD
AUD_IN Z PD I PD I PD
AUD_OUT Z PD Z PD Z PD
TX_DBG Z PU O
(1) I = input, O = output, Z = Hi-Z, – = no pull, PU = pullup, PD = pulldown, H = high, L = low

5.8.1.5 nSHUTD Requirements


PARAMETER MIN MAX UNIT
VIH Operation mode level (1) 1.42 1.98 V
VIL Shutdown mode level (1) 0 0.4 V
Minimum time for nSHUT_DOWN low to reset the device 5 ms
tr and tf Rise and fall times 20 µs
(1) An internal pulldown retains shutdown mode when no external signal is applied to this pin.

5.8.2 Clock Specifications

5.8.2.1 Slow Clock Requirements

An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the host or external crystal oscillator). The source must be a digital signal in the range of 0 to 1.8 V. The accuracy of the slow-clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of nSHUTD.

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CHARACTERISTICS CONDITION MIN TYP MAX UNIT
Input slow-clock frequency 32768 Hz
Input slow-clock accuracy
(Initial + temp + aging)		 Bluetooth ±250 ppm
tr and tf Input transition time tr and tf
(10% to 90%)		 200 ns
Frequency input duty cycle 15% 50% 85%
VIH Slow-clock input voltage limits Square wave,
DC-coupled		 0.65 × VDD_IO VDD_IO V peak
VIL 0 0.35 × VDD_IO V peak
Input impedance 1 MΩ
Input capacitance 5 pF

5.8.2.2 External Fast Clock Crystal Requirements and Operation

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CHARACTERISTICS CONDITION MIN TYP MAX UNIT
fin Supported crystal frequencies 26, 38.4 MHz
Frequency accuracy
(Initial + temperature + aging) 		±20 ppm
Crystal oscillator negative resistance 26 MHz, external capacitance = 8 pF 650 940 Ω
Iosc = 0.5 mA
26 MHz, external capacitance = 20 pF 490 710
Iosc = 2.2 mA

5.8.2.3 Fast Clock Source Requirements (–40°C to +85°C)

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CHARACTERISTICS CONDITION MIN TYP MAX UNIT
Supported frequencies, FREF 26, 38.4 MHz
Reference frequency accuracy Initial + temp + aging ±20 ppm
Fast-clock input voltage limits Square wave, DC-coupled VIL –0.2 0.37 V
VIH 1.0 2.1 V
Sine wave, AC-coupled 0.4 1.6 Vp-p
Sine wave, DC-coupled 0.4 1.6 Vp-p
Sine wave input limits, DC-coupled 0.0 1.6 V
Fast-clock input rise time
(as % of clock period)		 Square wave, DC-coupled 10%
Duty cycle 35% 50% 65%
Phase noise for 26 MHz @ offset = 1 kHz –123.4 dBc/Hz
@ offset = 10 kHz –133.4
@ offset = 100 kHz –138.4

5.8.3 Peripherals

5.8.3.1 UART

Figure 5-2 shows the UART timing diagram.

CC2564C td_uart_wrs064.gif Figure 5-2 UART Timing

Table 5-3 lists the UART timing characteristics.

Table 5-3 UART Timing Characteristics

SYMBOL CHARACTERISTICS CONDITION MIN TYP MAX UNIT
Baud rate 37.5 4000 kbps
Baud rate accuracy per byte Receive and transmit –2.5% 1.5%
Baud rate accuracy per bit Receive and transmit –12.5% 12.5%
t1 RTS low to RX_DATA on 0 2 µs
t2 RTS high to RX_DATA off Interrupt set to 1/4 FIFO 16 byte
t3 CTS low to TX_DATA on 0 2 µs
t4 CTS high to TX_DATA off Hardware flow control 1 byte
t6 CTS-high pulse width 1 bit

Figure 5-3 shows the UART data frame.

CC2564C td_uart2_wrs064.gif Figure 5-3 Data Frame

Table 5-4 describes the symbols used in Figure 5-3.

Table 5-4 Data Frame Key

SYMBOL DESCRIPTION
STR Start bit
D0...Dn Data bits (LSB first)
PAR Parity bit (optional)
STP Stop bit

5.8.3.2 PCM

Figure 5-4 shows the interface timing for the PCM.

CC2564C td_aud_wrs064.gif Figure 5-4 PCM Interface Timing

Table 5-5 lists the associated PCM master parameters.

Table 5-5 PCM Master

SYMBOL PARAMETER CONDITION MIN MAX UNIT
tclk Cycle time 244.14
(4.096 MHz)		 15625
(64 kHz)		 ns
tw High or low pulse width 50% of Tclk min ns
tis AUD_IN setup time 25 ns
tih AUD_IN hold time 0 ns
top AUD_OUT propagation time 40-pF load 0 10 ns
top FSYNC_OUT propagation time 40-pF load 0 10 ns

Table 5-6 lists the associated PCM slave parameters.

Table 5-6 PCM Slave

SYMBOL PARAMETER CONDITION MIN MAX UNIT
tclk Cycle time 66.67
(15 MHz)		 ns
tw High or low pulse width 40% of Tclk ns
Tis AUD_IN setup time 8 ns
tih AUD_IN hold time 0 ns
tis AUD_FSYNC setup time 8 ns
tih AUD_FSYNC hold time 0 ns
top AUD_OUT propagation time 40-pF load 0 21 ns

5.8.4 RF Performance

5.8.4.1 Bluetooth BR and EDR RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL and
38.4-MHz TCXO.

5.8.4.1.1 Bluetooth Receiver—In-Band Signals


CHARACTERISTICS CONDITION MIN TYP MAX BLUETOOTH SPECIFICATION UNIT
Operation frequency range 2402 2480 MHz
Channel spacing 1 MHz
Input impedance 50 Ω
Sensitivity, dirty TX on(1) GFSK, BER = 0.1% –91.5 –95 –70 dBm
π/4-DQPSK, BER = 0.01% –90.5 –94.5 –70
8DPSK, BER = 0.01% –81 –87.5 –70
BER error floor at sensitivity + 10 dB, dirty TX off π/4-DQPSK 1E–6 1E–7 1E–5
8DPSK 1E–6 1E–5
Maximum usable input power GFSK, BER = 0.1% –5 –20 dBm
π/4-DQPSK, BER = 0.1% –10
8DPSK, BER = 0.1% –10
Intermodulation characteristics Level of interferers (for n = 3, 4, and 5) –36 –30 –39 dBm
C/I performance(2)
Image = –1 MHz		 GFSK, cochannel 8 10 11 dB
EDR, cochannel π/4-DQPSK 9.5 11 13
8DPSK 16.5 20 21
GFSK, adjacent ±1 MHz –10 –5 0
EDR, adjacent ±1 MHz, (image) π/4-DQPSK –10 –5 0
8DPSK –5 –1 5
GFSK, adjacent +2 MHz –38 –35 –30
EDR, adjacent, +2 MHz π/4-DQPSK –38 –35 –30
8DPSK –38 –30 –25
GFSK, adjacent –2 MHz –28 –20 –20
EDR, adjacent –2 MHz π/4-DQPSK –28 –20 –20
8DPSK –22 –13 –13
GFSK, adjacent ≥ |±3| MHz –45 –43 –40
EDR, adjacent ≥ |±3| MHz π/4-DQPSK –45 –43 –40
8DPSK –44 –36 –33
RF return loss –10 dB
RX mode LO leakage Frf = (received RF – 0.6 MHz) –63 –58 dBm
(1) Sensitivity degradation up to 3 dB may occur for minimum and typical values where the Bluetooth frequency is a harmonic of the fast clock.
(2) Numbers show ratio of desired signal to interfering signal. Smaller numbers indicate better C/I performance.

5.8.4.1.2 Bluetooth Receiver—General Blocking


CHARACTERISTICS CONDITION MIN TYP UNIT
Blocking performance over full range, according to Bluetooth specification (1) 30 to 2000 MHz –6 dBm
2000 to 2399 MHz –6
2484 to 3000 MHz –6
3 to 12.75 GHz –6
(1) Exceptions are taken out of the total 24 allowed in the Bluetooth specification.

5.8.4.1.3 Bluetooth Transmitter—GFSK


CHARACTERISTICS MIN TYP MAX BLUETOOTH SPECIFICATION UNIT
Maximum RF output power(1) VDD_IN = VBAT 12 dBm
VDD_IN = external regulator to 1.8 V 10
Power variation over Bluetooth band –1 1 dB
Gain control range 30 dB
Power control step 5 2 to 8 dB
Adjacent channel power |M–N| = 2 –45 ≤ –20 dBm
Adjacent channel power |M–N| > 2 –50 ≤ –40 dBm
(1) To modify maximum output power, use an HCI VS command.

5.8.4.1.4 Bluetooth Transmitter—EDR


CHARACTERISTICS MIN TYP MAX BLUETOOTH SPECIFICATION UNIT
EDR output power(1) π/4-DQPSK VDD_IN = VBAT 5.5 dBm
VDD_IN = external regulator to 1.8 V 5.5
8DPSK VDD_IN = VBAT 5.5
VDD_IN = external regulator to 1.8 V 5.5
EDR relative power –2 1 –4 to +1 dB
Power variation over Bluetooth band –1 1 dB
Gain control range 30 dB
Power control step 5 2 to 8 dB
Adjacent channel power |M–N| = 1 –36 ≤ –26 dBc
Adjacent channel power |M–N| = 2 –30 ≤ –20 dBm
Adjacent channel power |M–N| > 2 –42 ≤ –40 dBm
(1) To modify maximum output power, use an NCI VS command.

5.8.4.1.5 Bluetooth Modulation—GFSK


CHARACTERISTICS CONDITION MIN TYP MAX BLUETOOTH SPECIFICATION UNIT
–20-dB bandwidth GFSK 925 ≤ 1000 kHz
F1 avg Modulation characteristics Δf1avg Mod data = 4 1 s,
4 0 s:
111100001111...		 165 140 to 175 kHz
F2 max Δf2max ≥ limit for at least 99.9% of all Δf2max Mod data = 1010101... 130 > 115 kHz
Δf2avg, Δf1avg 88% > 80%
Absolute carrier frequency drift DH1 –25 25 < ±25 kHz
DH3 and DH5 –35 35 < ±40
Drift rate 15 < 20 kHz/50 µs
Initial carrier frequency tolerance f0–fTX –75 +75 < ±75 kHz

5.8.4.1.6 Bluetooth Modulation—EDR


CHARACTERISTICS CONDITION MIN TYP MAX BLUETOOTH SPECIFICATION UNIT
Carrier frequency stability ±5 ≤ 10 kHz
Initial carrier frequency tolerance ±75 ±75 kHz
RMS DEVM (1) π/4-DQPSK 6% 20%
8DPSK 6% 13%
99% DEVM(1) π/4-DQPSK 30% 30%
8DPSK 20% 20%
Peak DEVM (1) π/4-DQPSK 14% 35%
8DPSK 16% 25%
(1) Maximum performance refers to maximum TX power.

5.8.4.1.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions


CHARACTERISTICS CONDITION TYP MAX UNIT
Second harmonic(1) Measured at maximum output power –14 –2 dBm
Third harmonic(1) –10 –6 dBm
Fourth harmonics(1) –19 –11 dBm
(1) Meets FCC and ETSI requirements with external filter shown in Figure 7-1.

5.8.4.2 Bluetooth low energy RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL and a
38.4-MHz TCXO.

5.8.4.2.1 Bluetooth low energy Receiver—In-Band Signals


CHARACTERISTIC CONDITION MIN TYP MAX BLUETOOTH
low energy SPECIFICATION		 UNIT
Operation frequency range 2402 2480 MHz
Channel spacing 2 MHz
Input impedance 50 Ω
Sensitivity, dirty TX on(1) PER = 30.8%; dirty TX on –96 ≤ –70 dBm
Maximum usable input power GMSK, PER = 30.8% –5 ≥ –10 dBm
Intermodulation characteristics Level of interferers
(for n = 3, 4, 5)		 –30 ≥ –50 dBm
C/I performance(2)
Image = –1 MHz		 GMSK, cochannel 8 ≤ 21 dB
GMSK, adjacent ±1 MHz –5 ≤ 15
GMSK, adjacent +2 MHz –45 ≤ –17
GMSK, adjacent –2 MHz –22 ≤ –15
GMSK, adjacent ≥ |±3| MHz –47 ≤ –27
RX mode LO leakage Frf = (received RF – 0.6 MHz) –63 dBm
(1) Sensitivity degradation up to 3 dB may occur where the Bluetooth low energy frequency is a harmonic of the fast clock.
(2) Numbers show wanted signal-to-interfering signal ratio. Smaller numbers indicate better C/I performance.

5.8.4.2.2 Bluetooth low energy Receiver—General Blocking


CHARACTERISTICS CONDITION MIN TYP BLUETOOTH
low energy
SPECIFICATION		 UNIT
Blocking performance over full range, according to Bluetooth low energy specification(1) 30 to 2000 MHz –15 ≥ –30 dBm
2000 to 2399 MHz –15 ≥ –35
2484 to 3000 MHz –15 ≥ –35
3 to 12.75 GHz –15 ≥ –30
(1) Exceptions are taken out of the total 10 allowed in the Bluetooth low energy specification.

5.8.4.2.3 Bluetooth low energy Transmitter



CHARACTERISTICS MIN TYP MAX BLUETOOTH
low energy
SPECIFICATION		 UNIT
RF output power VDD_IN = VBAT 12(1) ≤10 dBm
VDD_IN = External regulator to 1.8 V 10 ≤10
Power variation over Bluetooth low energy band 1 dB
Adjacent channel power |M-N| = 2 –45 ≤ –20 dBm
Adjacent channel power |M-N| > 2 –50 ≤ –30 dBm
(1) To achieve the Bluetooth low energy specification of 10-dBm maximum, an insertion loss of > 2 dB is assumed between the RF ball and the antenna. Otherwise, use an HCI VS command to modify the output power.

5.8.4.2.4 Bluetooth low energy Modulation


CHARACTERISTICS CONDITION MIN TYP MAX BLUETOOTH
low energy
SPECIFICATION		 UNIT
Δf1 avg Modulation characteristics Δf1avg Mod data = 4 1s, 4 0 s:
1111000011110000...		 240 250 260 225 to 275 kHz
Δf2 max Δf2max ≥ limit for at least 99.9% of all Δf2max Mod data = 1010101... 185 210 ≥ 185 kHz
Δf2avg, Δf1avg 0.85 0.9 ≥ 0.8
Absolute carrier frequency drift –25 25 ≤ ±50 kHz
Drift rate 15 ≤ 20 kHz/50 ms
Initial carrier frequency tolerance –75 75 ≤ ±100 kHz

5.8.4.2.5 Bluetooth low energy Transceiver, Out-Of-Band and Spurious Emissions


CHARACTERISTICS CONDITION TYP MAX UNIT
Second harmonic(1) Measured at maximum output power –14 –2 dBm
Third harmonic(1) –10 –6 dBm
Fourth harmonics(1) –19 –11 dBm
(1) Meets FCC and ETSI requirements with external filter shown in Figure 7-1.