ZHCSSS9A march 2023 – august 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1
PRODUCTION DATA
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
OUTPUT CONDITIONS | |||||
CL | Output load capacitance | 2 | 5 | pF | |
PCB CONNECTIVITY REQUIREMENTS | |||||
td(Trace Mismatch) | Propagation delay mismatch across all traces | 200 | ps |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1.8V Mode | |||||
DBTR1 | tc(TRC_CLK) | Cycle time, TRC_CLK | 6.83 | ns | |
DBTR2 | tw(TRC_CLKH) | Pulse width, TRC_CLK high | 2.66 | ns | |
DBTR3 | tw(TRC_CLKL) | Pulse width, TRC_CLK low | 2.66 | ns | |
DBTR4 | tosu(TRC_DATAV-TRC_CLK) | Output setup time, TRC_DATA valid to TRC_CLK edge | 0.85 | ns | |
DBTR5 | toh(TRC_CLK-TRC_DATAI) | Output hold time, TRC_CLK edge to TRC_DATA invalid | 0.85 | ns | |
DBTR6 | tosu(TRC_CTLV-TRC_CLK) | Output setup time, TRC_CTL valid to TRC_CLK edge | 0.85 | ns | |
DBTR7 | toh(TRC_CLK-TRC_CTLI) | Output hold time, TRC_CLK edge to TRC_CTL invalid | 0.85 | ns | |
3.3V Mode | |||||
DBTR1 | tc(TRC_CLK) | Cycle time, TRC_CLK | 8.78 | ns | |
DBTR2 | tw(TRC_CLKH) | Pulse width, TRC_CLK high | 3.64 | ns | |
DBTR3 | tw(TRC_CLKL) | Pulse width, TRC_CLK low | 3.64 | ns | |
DBTR4 | tosu(TRC_DATAV-TRC_CLK) | Output setup time, TRC_DATA valid to TRC_CLK edge | 1.10 | ns | |
DBTR5 | toh(TRC_CLK-TRC_DATAI) | Output hold time, TRC_CLK edge to TRC_DATA invalid | 1.10 | ns | |
DBTR6 | tosu(TRC_CTLV-TRC_CLK) | Output setup time, TRC_CTL valid to TRC_CLK edge | 1.10 | ns | |
DBTR7 | toh(TRC_CLK-TRC_CTLI) | Output hold time, TRC_CLK edge to TRC_CTL invalid | 1.10 | ns |