ZHCSSS9A march 2023 – august 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1
PRODUCTION DATA
This section describes connectivity requirements for package balls that have specific connectivity requirements and unused package balls.
All power pins must be supplied with the voltages specified in Section 7.4, Recommended Operating Conditions, unless otherwise specified.
For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball numbers.
AMB BALL NUMBER |
BALL NAME | CONNECTION REQUIREMENTS |
---|---|---|
B8 F15 |
MCU_ERRORn TRSTn |
Each of these balls must be connected to VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic low level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-down can be used to hold a valid logic low level if no PCB signal trace is connected to the ball. |
C13 E10 C12 E19 A14 A16 B14 |
EMU0 EMU1 MCU_RESETz RESET_REQz TCK TDI TMS |
Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-up can be used to hold a valid logic high level if no PCB signal trace is connected to the ball. |
E12 D9 D13 E13 |
MCU_I2C0_SCL MCU_I2C0_SDA WKUP_I2C0_SCL WKUP_I2C0_SDA |
Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high level. |
N21 N20 N19 N18 N17 P18 P19 P21 P22 R19 R20 R22 T22 R21 T20 T21 |
GPMC0_AD0 GPMC0_AD1 GPMC0_AD2 GPMC0_AD3 GPMC0_AD4 GPMC0_AD5 GPMC0_AD6 GPMC0_AD7 GPMC0_AD8 GPMC0_AD9 GPMC0_AD10 GPMC0_AD11 GPMC0_AD12 GPMC0_AD13 GPMC0_AD14 GPMC0_AD15 |
Each of these balls must be connected to the corresponding power supply(1) or VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high or low level as appropriate to select the desired device boot mode. |
A2 AA1 AB2 B1 J7 K8 L7 M8 N7 P8 L8 |
VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR_C |
If DDRSS is not used, each of these balls must be connected directly to VSS. |
N5 H7 M5 N2 M6 N6 J5 J2 J4 L4 J1 K5 K3 H2 L6 L2 K2 L5 M3 M2 K6 H3 P4 R7 H6 M1 L1 P3 P5 J6 N4 C2 F3 U1 W3 A5 B4 B6 D5 C5 C3 B2 A3 E2 F5 E6 G2 G6 G4 E4 D3 T6 T4 U5 R5 P2 R3 T2 U3 Y2 V2 V4 W5 Y4 AA3 AA5 AB4 D1 C1 G1 F1 R1 P1 W1 Y1 H5 N3 P6 |
DDR0_ACT_n DDR0_ALERT_n DDR0_CAS_n DDR0_PAR DDR0_RAS_n DDR0_WE_n DDR0_A0 DDR0_A1 DDR0_A2 DDR0_A3 DDR0_A4 DDR0_A5 DDR0_A6 DDR0_A7 DDR0_A8 DDR0_A9 DDR0_A10 DDR0_A11 DDR0_A12 DDR0_A13 DDR0_BA0 DDR0_BA1 DDR0_BG0 DDR0_BG1 DDR0_CAL0 DDR0_CK0 DDR0_CK0_n DDR0_CKE0 DDR0_CKE1 DDR0_CS0_n DDR0_CS1_n DDR0_DM0 DDR0_DM1 DDR0_DM2 DDR0_DM3 DDR0_DQ0 DDR0_DQ1 DDR0_DQ2 DDR0_DQ3 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_DQ8 DDR0_DQ9 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQ16 DDR0_DQ17 DDR0_DQ18 DDR0_DQ19 DDR0_DQ20 DDR0_DQ21 DDR0_DQ22 DDR0_DQ23 DDR0_DQ24 DDR0_DQ25 DDR0_DQ26 DDR0_DQ27 DDR0_DQ28 DDR0_DQ29 DDR0_DQ30 DDR0_DQ31 DDR0_DQS0 DDR0_DQS0_n DDR0_DQS1 DDR0_DQS1_n DDR0_DQS2 DDR0_DQS2_n DDR0_DQS2 DDR0_DQS2_n DDR0_ODT0 DDR0_ODT1 DDR0_RESET0_n |
If DDRSS is not used, leave unconnected.Note: The DDR0 pins in this list can only be left unconnected when VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0 pins must be connected as defined in the DDR Board Design and Layout Guidelines, when VDDS_DDR and VDDS_DDR_C are connected to a power source. |
T9 T10 U10 |
VDDA_CORE_USB VDDA_1P8_USB VDDA_3P3_USB |
USB0 and USB1 share these power rails, so each of these balls must be connected to valid power sources when either USB0 or USB1 is used.If USB0 and USB1 are not used, each of these balls must be connected directly to VSS. |
AA10 AA9 W10 V8 Y11 Y10 U7 V6 |
USB0_DM USB0_DP USB0_RCALIB USB0_VBUS USB1_DM USB1_DP USB1_RCALIB USB1_VBUS |
If USB0 or USB1 is not used, leave the respective DM, DP, and VBUS balls unconnected.Note: The USB0_RCALIB and USB1_RCALIB pins can only be left unconnected when VDDA_CORE_USB, VDDA_1P8_USB, and VDDA_3P3_USB are connected to VSS. The USB0_RCALIB and USB1_RCALIB pins must be connected to VSS through separate appropriate external resistors when VDDA_CORE_USB, VDDA_1P8_USB, and VDDA_3P3_USB are connected to power sources. |
T11 T12 |
VDDA_CORE_CSIRX0 VDDA_1P8_CSIRX0 |
If CSIRX0 is not used and the device boundary scan function is required, each of these balls must be connected to valid power sources.If CSIRX0 is not used and the device boundary scan function is not required, each of these balls can alternatively be connected directly to VSS. |
AB14 AB13 W12 W13 Y13 Y14 AA13 AA12 AB11 AB10 V10 |
CSI0_RXCLKN CSI0_RXCLKP CSI0_RXN0 CSI0_RXP0 CSI0_RXN1 CSI0_RXP1 CSI0_RXN2 CSI0_RXP2 CSI0_RXN3 CSI0_RXP3 CSI0_RXRCALIB |
If CSIRX0 is not used, leave unconnected. |
H12 | VMON_VSYS | If VMON_VSYS is not used, this ball must be connected directly to VSS. |
F12 | VMON_1P8_SOC | If VMON_1P8_SOC is not used to monitor the SOC power rail, this ball must remain connected to a 1.8-V power rail. |
F9 | VMON_3P3_SOC | If VMON_3P3_SOC is not used to monitor the SOC power rail, this ball must remain connected to a 3.3-V power rail or connected directly to VSS. |
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This can be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are recommended to hold a valid logic level on balls with external connections.
Many of the device IOs are turned off by default and external pull resistors may be required to hold inputs of any attached device in a valid logic state until software initializes the respective IOs. The state of configurable device IOs are defined in the BALL STATE DURING RESET RX/TX/PULL and BALL STATE AFTER RESET RX/TX/PULL columns of the Pin Attributes table. Any IO with its input buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input buffer (RX) turned on shall never be allowed to float to any potential between VILSS and VIHSS. The input buffer can enter a high-current state which could damage the IO cell if allowed to float between these levels.