ZHCSSS9A march 2023 – august 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1
PRODUCTION DATA
Table 7-83, Figure 7-69, Table 7-84, and Figure 7-70 present timing requirements and switching characteristics for MMC0 – High Speed SDR Mode.
NO. | IO Operating Voltage |
MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
HSSDR1 | tsu(cmdV-clkH) | Setup time, MMC0_CMD valid before MMC0_CLK rising edge | 1.8 V | 2.15 | ns | |
3.3 V | 2.24 | ns | ||||
HSSDR2 | th(clkH-cmdV) | Hold time, MMC0_CMD valid after MMC0_CLK rising edge | 1.8 V | 1.27 | ns | |
3.3 V | 1.66 | ns | ||||
HSSDR3 | tsu(dV-clkH) | Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge | 1.8 V | 2.15 | ns | |
3.3 V | 2.24 | ns | ||||
HSSDR4 | th(clkH-dV) | Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge | 1.8 V | 1.27 | ns | |
3.3 V | 1.66 | ns |
NO. | PARAMETER | IO Operating Voltage |
MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC0_CLK | 50 | MHz | |||
HSSDR5 | tc(clk) | Cycle time, MMC0_CLK | 20 | ns | ||
HSSDR6 | tw(clkH) | Pulse duration, MMC0_CLK high | 9.2 | ns | ||
HSSDR7 | tw(clkL) | Pulse duration, MMC0_CLK low | 9.2 | ns | ||
HSSDR8 | td(clkL-cmdV) | Delay time, MMC0_CLK falling edge to MMC0_CMD transition | 1.8 V | -1.55 | 3.05 | ns |
3.3 V | -1.8 | 2.2 | ns | |||
HSSDR9 | td(clkL-dV) | Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition | 1.8 V | -1.55 | 3.05 | ns |
3.3 V | -1.8 | 2.2 | ns |