ZHCSSS9A march   2023  – august 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      12
      2.      13
    3. 6.3 Signal Descriptions
      1.      15
      2. 6.3.1  CPSW3G
        1. 6.3.1.1 MAIN Domain
          1.        18
          2.        19
          3.        20
          4.        21
      3. 6.3.2  CPTS
        1. 6.3.2.1 MAIN Domain
          1.        24
      4. 6.3.3  CSI-2
        1. 6.3.3.1 MAIN Domain
          1.        27
      5. 6.3.4  DDRSS
        1. 6.3.4.1 MAIN Domain
          1.        30
      6. 6.3.5  DSS
        1. 6.3.5.1 MAIN Domain
          1.        33
      7. 6.3.6  ECAP
        1. 6.3.6.1 MAIN Domain
          1.        36
          2.        37
          3.        38
      8. 6.3.7  Emulation and Debug
        1. 6.3.7.1 MAIN Domain
          1.        41
        2. 6.3.7.2 MCU Domain
          1.        43
      9. 6.3.8  EPWM
        1. 6.3.8.1 MAIN Domain
          1.        46
          2.        47
          3.        48
          4.        49
      10. 6.3.9  EQEP
        1. 6.3.9.1 MAIN Domain
          1.        52
          2.        53
          3.        54
      11. 6.3.10 GPIO
        1. 6.3.10.1 MAIN Domain
          1.        57
          2.        58
        2. 6.3.10.2 MCU Domain
          1.        60
      12. 6.3.11 GPMC
        1. 6.3.11.1 MAIN Domain
          1.        63
      13. 6.3.12 I2C
        1. 6.3.12.1 MAIN Domain
          1.        66
          2.        67
          3.        68
          4.        69
        2. 6.3.12.2 MCU Domain
          1.        71
        3. 6.3.12.3 WKUP Domain
          1.        73
      14. 6.3.13 MCAN
        1. 6.3.13.1 MAIN Domain
          1.        76
        2. 6.3.13.2 MCU Domain
          1.        78
          2.        79
      15. 6.3.14 MCASP
        1. 6.3.14.1 MAIN Domain
          1.        82
          2.        83
          3.        84
      16. 6.3.15 MCSPI
        1. 6.3.15.1 MAIN Domain
          1.        87
          2.        88
          3.        89
        2. 6.3.15.2 MCU Domain
          1.        91
          2.        92
      17. 6.3.16 MDIO
        1. 6.3.16.1 MAIN Domain
          1.        95
      18. 6.3.17 MMC
        1. 6.3.17.1 MAIN Domain
          1.        98
          2.        99
          3.        100
      19. 6.3.18 OSPI
        1. 6.3.18.1 MAIN Domain
          1.        103
      20. 6.3.19 Power Supply
        1.       105
      21. 6.3.20 Reserved
        1.       107
      22. 6.3.21 System and Miscellaneous
        1. 6.3.21.1 Boot Mode Configuration
          1. 6.3.21.1.1 MAIN Domain
            1.         111
        2. 6.3.21.2 Clock
          1. 6.3.21.2.1 MCU Domain
            1.         114
          2. 6.3.21.2.2 WKUP Domain
            1.         116
        3. 6.3.21.3 System
          1. 6.3.21.3.1 MAIN Domain
            1.         119
          2. 6.3.21.3.2 MCU Domain
            1.         121
          3. 6.3.21.3.3 WKUP Domain
            1.         123
        4. 6.3.21.4 VMON
          1.        125
      23. 6.3.22 TIMER
        1. 6.3.22.1 MAIN Domain
          1.        128
        2. 6.3.22.2 MCU Domain
          1.        130
        3. 6.3.22.3 WKUP Domain
          1.        132
      24. 6.3.23 UART
        1. 6.3.23.1 MAIN Domain
          1.        135
          2.        136
          3.        137
          4.        138
          5.        139
          6.        140
          7.        141
        2. 6.3.23.2 MCU Domain
          1.        143
        3. 6.3.23.3 WKUP Domain
          1.        145
      25. 6.3.24 USB
        1. 6.3.24.1 MAIN Domain
          1.        148
          2.        149
    4. 6.4 Pin Connectivity Requirements
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.7.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 7.7.4 Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 7.7.5 SDIO Electrical Characteristics
      6. 7.7.6 LVCMOS Electrical Characteristics
      7. 7.7.7 CSI-2 (D-PHY) Electrical Characteristics
      8. 7.7.8 USB2PHY Electrical Characteristics
      9. 7.7.9 DDR Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics for AMB Package
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Requirements
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Power Supply Sequencing
          1. 7.10.2.2.1 Power-Up Sequencing
          2. 7.10.2.2.2 Power-Down Sequencing
          3. 7.10.2.2.3 Partial IO Power Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Error Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input Clocks / Oscillators
          1. 7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 7.10.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 WKUP_LFOSC0 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 7.10.5 Peripherals
        1. 7.10.5.1  CPSW3G
          1. 7.10.5.1.1 CPSW3G MDIO Timing
          2. 7.10.5.1.2 CPSW3G RMII Timing
          3. 7.10.5.1.3 CPSW3G RGMII Timing
        2. 7.10.5.2  CPTS
        3. 7.10.5.3  CSI-2
        4. 7.10.5.4  DDRSS
        5. 7.10.5.5  DSS
        6. 7.10.5.6  ECAP
        7. 7.10.5.7  Emulation and Debug
          1. 7.10.5.7.1 Trace
          2. 7.10.5.7.2 JTAG
        8. 7.10.5.8  EPWM
        9. 7.10.5.9  EQEP
        10. 7.10.5.10 GPIO
        11. 7.10.5.11 GPMC
          1. 7.10.5.11.1 GPMC and NOR Flash — Synchronous Mode
          2. 7.10.5.11.2 GPMC and NOR Flash — Asynchronous Mode
          3. 7.10.5.11.3 GPMC and NAND Flash — Asynchronous Mode
        12. 7.10.5.12 I2C
        13. 7.10.5.13 MCAN
        14. 7.10.5.14 MCASP
        15. 7.10.5.15 MCSPI
          1. 7.10.5.15.1 MCSPI — Controller Mode
          2. 7.10.5.15.2 MCSPI — Peripheral Mode
        16. 7.10.5.16 MMCSD
          1. 7.10.5.16.1 MMC0 - eMMC/SD/SDIO Interface
            1. 7.10.5.16.1.1  Legacy SDR Mode
            2. 7.10.5.16.1.2  High Speed SDR Mode
            3. 7.10.5.16.1.3  HS200 Mode
            4. 7.10.5.16.1.4  Default Speed Mode
            5. 7.10.5.16.1.5  High Speed Mode
            6. 7.10.5.16.1.6  UHS–I SDR12 Mode
            7. 7.10.5.16.1.7  UHS–I SDR25 Mode
            8. 7.10.5.16.1.8  UHS–I SDR50 Mode
            9. 7.10.5.16.1.9  UHS–I DDR50 Mode
            10. 7.10.5.16.1.10 UHS–I SDR104 Mode
          2. 7.10.5.16.2 MMC1/MMC2 - SD/SDIO Interface
            1. 7.10.5.16.2.1 Default Speed Mode
            2. 7.10.5.16.2.2 High Speed Mode
            3. 7.10.5.16.2.3 UHS–I SDR12 Mode
            4. 7.10.5.16.2.4 UHS–I SDR25 Mode
            5. 7.10.5.16.2.5 UHS–I SDR50 Mode
            6. 7.10.5.16.2.6 UHS–I DDR50 Mode
            7. 7.10.5.16.2.7 UHS–I SDR104 Mode
        17. 7.10.5.17 OSPI
          1. 7.10.5.17.1 OSPI0 PHY Mode
            1. 7.10.5.17.1.1 OSPI0 With PHY Data Training
            2. 7.10.5.17.1.2 OSPI0 Without Data Training
              1. 7.10.5.17.1.2.1 OSPI0 PHY SDR Timing
              2. 7.10.5.17.1.2.2 OSPI0 PHY DDR Timing
          2. 7.10.5.17.2 OSPI0 Tap Mode
            1. 7.10.5.17.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.17.2.2 OSPI0 Tap DDR Timing
        18. 7.10.5.18 Timers
        19. 7.10.5.19 UART
        20. 7.10.5.20 USB
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A53 Subsystem
      2. 8.2.2 Device/Power Manager
      3. 8.2.3 MCU Arm Cortex-R5F Subsystem
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 C7xV-256 Deep Learning Accelerator
      2. 8.3.2 Vision Pre-processing Accelerator
      3. 8.3.3 JPEG Encoder
      4. 8.3.4 Video Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 Dual Clock Comparator (DCC)
      2. 8.4.2 Data Movement Subsystem (DMSS)
      3. 8.4.3 Memory Cyclic Redundancy Check (MCRC)
      4. 8.4.4 Peripheral DMA Controller (PDMA)
      5. 8.4.5 Real-Time Clock (RTC)
    5. 8.5 Peripherals
      1. 8.5.1  Gigabit Ethernet Switch (CPSW3G)
      2. 8.5.2  Camera Serial Interface Receiver (CSI_RX_IF)
      3. 8.5.3  Display Subsystem (DSS)
      4. 8.5.4  Enhanced Capture (ECAP)
      5. 8.5.5  Error Location Module (ELM)
      6. 8.5.6  Enhanced Pulse Width Modulation (EPWM)
      7. 8.5.7  Error Signaling Module (ESM)
      8. 8.5.8  Enhanced Quadrature Encoder Pulse (EQEP)
      9. 8.5.9  General-Purpose Interface (GPIO)
      10. 8.5.10 General-Purpose Memory Controller (GPMC)
      11. 8.5.11 Global Timebase Counter (GTC)
      12. 8.5.12 Inter-Integrated Circuit (I2C)
      13. 8.5.13 Modular Controller Area Network (MCAN)
      14. 8.5.14 Multichannel Audio Serial Port (MCASP)
      15. 8.5.15 Multichannel Serial Peripheral Interface (MCSPI)
      16. 8.5.16 Multi-Media Card Secure Digital (MMCSD)
      17. 8.5.17 Octal Serial Peripheral Interface (OSPI)
      18. 8.5.18 Timers
      19. 8.5.19 Universal Asynchronous Receiver/Transmitter (UART)
      20. 8.5.20 Universal Serial Bus Subsystem (USBSS)
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply
        1. 9.1.1.1 Power Supply Designs
        2. 9.1.1.2 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG, EMU, and TRACE
      4. 9.1.4 Unused Pins
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 DDR Board Design and Layout Guidelines
      2. 9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal SPI devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
    3. 9.3 Clock Routing Guidelines
      1. 9.3.1 Oscillator Routing
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • AMB|484
散热焊盘机械数据 (封装 | 引脚)
订购信息
7.10.5.11.1 GPMC and NOR Flash — Synchronous Mode

Table 7-63 and Table 7-64 present timing requirements and switching characteristics for GPMC and NOR Flash - Synchronous Mode.

Table 7-63 GPMC and NOR Flash Timing Requirements — Synchronous Mode see Figure 7-46, Figure 7-47, and Figure 7-50
NO. PARAMETER DESCRIPTION MODE(4) MIN MAX MIN MAX UNIT
GPMC_FCLK = 100 MHz(1) GPMC_FCLK = 133 MHz(1)
F12 tsu(dV-clkH) Setup time, input data GPMC_AD[15:0] valid before output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 1.61 0.92 ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 0.86 3.41 ns
F13 th(clkH-dV) Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 2.09 2.09 ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 2.09 2.09 ns
F21 tsu(waitV-clkH) Setup time, input wait GPMC_WAIT[j](2)(3) valid before output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 1.61 0.92 ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 0.86 3.41 ns
F22 th(clkH-waitV) Hold time, input wait GPMC_WAIT[j](2)(3) valid after output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 2.09 2.09 ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 2.09 2.09 ns
(1) GPMC_FCLK select
  • gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK
  • gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK
(2) In GPMC_WAIT[j], j is equal to 0 or 1.
(3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-Purpose Memory Controller (GPMC) section in the device TRM.
(4) For div_by_1_mode:
  • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
    • GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:
  • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
    • GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX:
  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:
  • GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)
Table 7-64 GPMC and NOR Flash Switching Characteristics – Synchronous Mode see Figure 7-46, Figure 7-47, Figure 7-48, Figure 7-49, and Figure 7-50
NO.(2) PARAMETER DESCRIPTION MODE(16) MIN MAX MIN MAX UNIT
100 MHz 133 MHz
F0 1 / tc(clk) Period, output clock GPMC_CLK(15) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 10.00 7.52 ns
F1 tw(clkH) Typical pulse duration, output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 0.475P - 0.3(14) 0.475P - 0.3(14) ns
F1 tw(clkL) Typical pulse duration, output clock GPMC_CLK low div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 0.475P - 0.3(14) 0.475P - 0.3(14) ns
F2 td(clkH-csnV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition(13) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay		 F - 2.2 (5) F + 3.75 F - 2.2 (5) F + 3.75 ns
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid(13) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay		 E - 2.2 (4) E + 3.18 E - 2.2 (4) E + 4.5 ns
F4 td(aV-clk) Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 B - 2.3 (2) B + 4.5 B - 2.3 (2) B + 4.5 ns
F5 td(clkH-aIV) Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 -2.3 4.5 -2.3 4.5 ns
F6 td(be[x]nV-clk) Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 B - 2.3 (2) B + 1.9 B - 2.3 (2) B + 1.9 ns
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(10) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 D - 2.3(3) D + 1.9 D - 2.3 (3) D + 1.9 ns
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(11) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 D - 2.3 (3) D + 1.9 D - 2.3 (3) D + 1.9 ns
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 D - 2.3 (3) D + 1.9 D - 2.3 (3) D + 1.9 ns
F8 td(clkH-advn) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay		 G - 2.3(6) G + 4.5 G - 2.3 (6) G + 4.5 ns
F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay		 D - 2.3 (3) D + 4.5 D - 2.3 (3) D + 4.5 ns
F10 td(clkH-oen) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay		 H - 2.3 (7) H + 3.5 H - 2.3 (7) H + 3.5 ns
F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay		 H - 2.3 (7) H + 3.5 H - 2.3 (7) H + 3.5 ns
F14 td(clkH-wen) Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay		 I - 2.3 (8) I + 4.5 I - 2.3 (8) I + 4.5 ns
F15 td(clkH-do) Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(10) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns
F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(11) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns
F15 td(clkL-do). Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns
F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(10) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns
F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(11) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns
F17 td(clkL-be[x]n). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns
F18 tw(csnV) Pulse duration, output chip select GPMC_CSn[i](13) low Read A A ns
Write A A ns
F19 tw(be[x]nV) Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low Read C C ns
Write C C ns
F20 tw(advnV) Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low Read K K ns
Write K K ns
(2) B = ClkActivationTime × GPMC_FCLK(14)
(3) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(4) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) For csn falling edge (CS activated):
  • Case GPMCFCLKDIVIDER = 0:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
    • F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(6) For ADV falling edge (ADV activated):
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(7) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For WE falling edge (WE activated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK (14)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) J = GPMC_FCLK(14)
(10) First transfer only for CLK DIV 1 mode.
(11) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(12) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
(14) P = GPMC_CLK period in ns
(15) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(16) For div_by_1_mode:
  • GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
    • GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:
  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:
  • GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

For no extra_delay:
  • GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
  • GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
  • GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
  • GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
GUID-15E6DF0F-CED7-41F6-9B7C-2CB448FFBD55-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-46 GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
GUID-BF774493-D226-4746-84E1-EC253E2F6E02-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-47 GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
GUID-303303DA-BB3E-4C9A-90F8-0578C57AA6AD-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-48 GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
GUID-7E193CA0-1BFB-4848-BF90-F82174643C4A-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-49 GPMC and Multiplexed NOR Flash — Synchronous Burst Read
GUID-D3F03E5A-08AB-4266-B4A5-94F63115813E-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-50 GPMC and Multiplexed NOR Flash — Synchronous Burst Write