ZHCSDC3 数据表 | 德州仪器 TI.com.cn

ZHCSDC3E June 2014 – January 2019 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

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Table 5-43 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode

NO.	PARAMETER			OPP100		OPP50		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	UNIT
FA0	t_w(be[x]nV)	Pulse duration, output lower-byte enable and command latch enable gpmc_be0n_cle, output upper-byte enable gpmc_be1n valid time	Read		N⁽¹⁾		N⁽¹⁾	ns
FA0	t_w(be[x]nV)		Write		N⁽¹⁾		N⁽¹⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select gpmc_csn[x]⁽²⁾ low	Read		A⁽³⁾		A⁽³⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select gpmc_csn[x]⁽²⁾ low	Write		A⁽³⁾		A⁽³⁾	ns
FA3	t_{d(csnV-advnIV)}	Delay time, output chip select gpmc_csn[x]⁽²⁾ valid to output address valid and address latch enable gpmc_advn_ale invalid	Read	B⁽⁴⁾ – 0.2	B⁽⁴⁾ + 2.0	B⁽⁴⁾ – 0.2	B⁽⁴⁾ + 2.0	ns
FA3	t_{d(csnV-advnIV)}		Write	B⁽⁴⁾ – 0.2	B⁽⁴⁾ + 2.0	B⁽⁴⁾ – 0.2	B⁽⁴⁾ + 2.0	ns
FA4	t_{d(csnV-oenIV)}	Delay time, output chip select gpmc_csn[x]⁽²⁾ valid to output enable gpmc_oen invalid (Single read)		C⁽⁵⁾ – 0.2	C⁽⁵⁾ + 2.0	C⁽⁵⁾ – 0.2	C⁽⁵⁾ + 2.0	ns
FA9	t_d(aV-csnV)	Delay time, output address gpmc_a[27:1] valid to output chip select gpmc_csn[x]⁽²⁾ valid		J⁽⁶⁾ – 0.2	J⁽⁶⁾ + 2.0	J⁽⁶⁾ – 0.2	J⁽⁶⁾ + 2.0	ns
FA10	t_{d(be[x]nV-csnV)}	Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle, output upper-byte enable gpmc_be1n valid to output chip select gpmc_csn[x]⁽²⁾ valid		J⁽⁶⁾ – 0.2	J⁽⁶⁾ + 2.0	J⁽⁶⁾ – 0.2	J⁽⁶⁾ + 2.0	ns
FA12	t_{d(csnV-advnV)}	Delay time, output chip select gpmc_csn[x]⁽²⁾ valid to output address valid and address latch enable gpmc_advn_ale valid		K⁽⁷⁾ – 0.2	K⁽⁷⁾ + 2.0	K⁽⁷⁾ – 0.2	K⁽⁷⁾ + 2.0	ns
FA13	t_d(csnV-oenV)	Delay time, output chip select gpmc_csn[x]⁽²⁾ valid to output enable gpmc_oen valid		L⁽⁸⁾ – 0.2	L⁽⁸⁾ + 2.0	L ⁽⁸⁾ – 0.2	L⁽⁸⁾ + 2.0	ns
FA16	t_w(aIV)	Pulse durationm output address gpmc_a[26:1] invalid between 2 successive read and write accesses		G⁽⁹⁾		G⁽⁹⁾		ns
FA18	t_{d(csnV-oenIV)}	Delay time, output chip select gpmc_csn[x]⁽²⁾ valid to output enable gpmc_oen invalid (Burst read)		I⁽¹⁰⁾ – 0.2	I⁽¹⁰⁾ + 2.0	I⁽¹⁰⁾ – 0.2	I⁽¹⁰⁾ + 2.0	ns
FA20	t_w(aV)	Pulse duration, output address gpmc_a[27:1] valid — 2nd, 3rd, and 4th accesses		D⁽¹¹⁾		D⁽¹¹⁾		ns
FA25	t_d(csnV-wenV)	Delay time, output chip select gpmc_csn[x]⁽²⁾ valid to output write enable gpmc_wen valid		E⁽¹²⁾ – 0.2	E⁽¹²⁾ + 2.0	E⁽¹²⁾ – 0.2	E⁽¹²⁾ + 2.0	ns
FA27	t_{d(csnV-wenIV)}	Delay time, output chip select gpmc_csn[x]⁽²⁾ valid to output write enable gpmc_wen invalid		F⁽¹³⁾ – 0.2	F⁽¹³⁾ + 2.0	F⁽¹³⁾ – 0.2	F⁽¹³⁾ + 2.0	ns
FA28	t_d(wenV-dV)	Delay time, output write enable gpmc_ wen valid to output data gpmc_ad[15:0] valid			2.8		5	ns
FA29	t_d(dV-csnV)	Delay time, output data gpmc_ad[15:0] valid to output chip select gpmc_csn[x]⁽²⁾ valid		J⁽⁶⁾ – 0.2	J⁽⁶⁾ + 2.8	J⁽⁶⁾ – 0.2	J⁽⁶⁾ + 2.8	ns
FA37	t_d(oenV-aIV)	Delay time, output enable gpmc_oen valid to output address gpmc_ad[15:0] phase end			2.8		2.8	ns

For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: N = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: N = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: A = (CSWrOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
with n being the page burst access number
For reading: B = ((ADVRdOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
For writing: B = ((ADVWrOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
C = ((OEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾
K = ((ADVOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
L = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
G = Cycle2CycleDelay × GPMC_FCLK⁽¹⁴⁾
I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
E = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
F = ((WEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

AM4372 AM4376 AM4377 AM4378 AM4379 gpmc6_sprs851.gif

A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.

C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.

Figure 5-38 GPMC and NOR Flash—Asynchronous Read—Single Word

AM4372 AM4376 AM4377 AM4378 AM4379 gpmc7_sprs851.gif

A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.

Figure 5-39 GPMC and NOR Flash—Asynchronous Read—32-Bit

AM4372 AM4376 AM4377 AM4378 AM4379 gpmc8_sprs851.gif

A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.

C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field.

D. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.

Figure 5-40 GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-Bit

AM4372 AM4376 AM4377 AM4378 AM4379 gpmc9_sprs851.gif

A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.

Figure 5-41 GPMC and NOR Flash—Asynchronous Write—Single Word

AM4372 AM4376 AM4377 AM4378 AM4379 gpmc10_sprs851.gif

A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.

Figure 5-42 GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word

AM4372 AM4376 AM4377 AM4378 AM4379 gpmc11_sprs851.gif

A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.

Figure 5-43 GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word