ZHCSPA8 March   2024 AFE7950-SP

PRODMIX  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Transmitter Electrical Characteristics
    6. 4.6  RF ADC Electrical Characteristics
    7. 4.7  PLL/VCO/Clock Electrical Characteristics
    8. 4.8  Digital Electrical Characteristics
    9. 4.9  Power Supply Electrical Characteristics
    10. 4.10 Timing Requirements
    11. 4.11 Switching Characteristics
    12. 4.12 Typical Characteristics
      1. 4.12.1  TX Typical Characteristics 800MHz
      2. 4.12.2  TX Typical Characteristics at 1.8GHz
      3. 4.12.3  TX Typical Characteristics at 2.6GHz
      4. 4.12.4  TX Typical Characteristics at 3.5GHz
      5. 4.12.5  TX Typical Characteristics at 4.9GHz
      6. 4.12.6  TX Typical Characteristics at 8.1GHz
      7. 4.12.7  TX Typical Characteristics at 9.6GHz
      8. 4.12.8  RX Typical Characteristics at 800MHz
      9. 4.12.9  RX Typical Characteristics at 1.75-1.9GHz
      10. 4.12.10 RX Typical Characteristics at 2.6GHz
      11. 4.12.11 RX Typical Characteristics at 3.5GHz
      12. 4.12.12 RX Typical Characteristics at 4.9GHz
      13. 4.12.13 RX Typical Characteristics at 8.1GHz
      14. 4.12.14 RX Typical Characteristics at 9.6GHz
  6. 5Device and Documentation Support
    1. 5.1 接收文档更新通知
    2. 5.2 支持资源
    3. 5.3 Trademarks
    4. 5.4 静电放电警告
    5. 5.5 术语表
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

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4.10 Timing Requirements

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
MIN NOM MAX UNIT
Timing: SYSREF+/-
ts(SYSREF) Setup Time, SYSREF+/- Valid to Rising Edge of CLK+/- 50 ps
th(SYSREF) Hold Time, SYSREF+/- Valid after Rising Edge of CLK+/- 50 ps
Timing: Serial ports
ts(SENB) Setup Time, SENB to Rising Edge of SCLK 15 ns
th(SENB) Hold Time, SENB after last Rising Edge of SCLK (1) 5 + tSCLK ns
ts(SDIO) Setup Time, SDIO valid to Rising Edge of SCLK 15 ns
th(SDIO) Hold Time, SDIO valid after Rising Edge of SCLK 5 ns
t(SCLK)_W Minimum SCLK period: registers write 25 ns
t(SCLK)_R Minimum SCLK period: registers read 50 ns
t(SCLK)_R SCLK period: temp sensor (2) 1000 ns
td(data_out) Minimum Data Output delay after Falling Edge of SCLK 0 ns
Maximum Data Output delay after Falling Edge of SCLK 15 ns
tRESET Minimum RESETZ Pulse Width 1 ms
(1) SDEN\\ need to be held one more extra clock cycle with the last SCLK edge
(2) Temp sensor requires a maximum of 1MHz SCLK cycle.