ZHCSM18A January   2023  – December 2023 ADS9815 , ADS9817

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
        4. 6.3.1.4 Gain Error Calibration
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Sample Synchronization
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Clock Output
        2. 6.3.6.2 ADC Output Data Randomizer
        3. 6.3.6.3 Test Patterns for Data Interface
          1. 6.3.6.3.1 User-Defined Test Pattern
          2. 6.3.6.3.2 User-Defined Alternating Test Pattern
          3. 6.3.6.3.3 Ramp Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down
      2. 6.4.2 Reset
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) System
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 CMOS Data Interface
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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6.3.1.2 Programmable Gain Amplifier (PGA)

The ADS981x features a PGA at every analog input channel. The PGA supports single-ended and differential inputs with a bipolar signal swing. Table 6-1 lists the supported analog input ranges. The analog input range can be configured independently for each channel by using the RANGE_CHx register fields in address 0xC2 and address 0xC3.

Table 6-1 Analog Input Ranges
DIFFERENTIAL INPUTS SINGLE-ENDED INPUTS RANGE_CHx CONFIGURATION
±12 V ±12 V 5
±10 V ±10 V 4
±7 V ±7 V 3
±5 V ±5 V 0
±3.5 V ±3.5 V 1
±2.5 V ±2.5 V 2

Each analog input channel features an antialiasing, low-pass filter (LPF) at the output of the PGA. Table 6-2 lists the various programmable LPF options available in the ADS981x corresponding to the analog input range. Figure 5-14 and Figure 5-15 illustrate the frequency responses for low-bandwidth and wide-bandwidth LPF configurations. The analog input bandwidth for the eight analog input channels can be can be selected using the ANA_BW[7:0] bits in address 0xC0 of register bank 1.

Table 6-2 Low-Pass Filter Corner Frequency
LPF ANALOG INPUT RANGE CORNER FREQUENCY (–3 dB)
Low-bandwidth All input ranges 21.2 kHz
Wide-bandwidth ±12 V 375 kHz
±10 V 385 kHz
±7 V 400 kHz
±5 V 320 kHz
±3.5 V 240 kHz
±2.5 V 185 kHz