ZHCSM18A January   2023  – December 2023 ADS9815 , ADS9817

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
        4. 6.3.1.4 Gain Error Calibration
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Sample Synchronization
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Clock Output
        2. 6.3.6.2 ADC Output Data Randomizer
        3. 6.3.6.3 Test Patterns for Data Interface
          1. 6.3.6.3.1 User-Defined Test Pattern
          2. 6.3.6.3.2 User-Defined Alternating Test Pattern
          3. 6.3.6.3.3 Ramp Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down
      2. 6.4.2 Reset
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) System
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 CMOS Data Interface
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.1 Register Bank 0

Figure 7-1 Register Bank 0 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
00h RESERVED SPI_MODE SPI_RD_EN RESET
01h RESERVED DAISY_CHAIN_LEN RESERVED
03h RESERVED REG_BANK_SEL
04h RESERVED INIT_1
06h REG_00H_READBACK
Table 7-1 Register Section/Block Access Type Codes
Access Type Code Description
R R Read
W W Write
R/W R/W Read or write
Reset or Default Value
-n Value after reset or the default value

7.1.1 Register 00h (offset = 0h) [reset = 0h]

Figure 7-2 Register 00h
15 14 13 12 11 10 9 8
RESERVED
W-0h
7 6 5 4 3 2 1 0
RESERVED SPI_MODE SPI_RD_EN RESET
W-0h W-0h W-0h W-0h
Figure 7-3 Register 00h Field Descriptions
Bit Field Type Reset Description
15-3 RESERVED W 0h Reserved. Do not change from the default reset value.
2 SPI_MODE W 0h Select between legacy SPI mode and daisy-chain SPI mode for the configuration interface for register access.
0 : Daisy-chain SPI mode
1 : Legacy SPI mode
1 SPI_RD_EN W 0h Enable register read access in legacy SPI mode. This bit has no effect in daisy-chain SPI mode.
0 : Register read disabled
1 : Register read enabled
0 RESET W 0h ADC reset control.
0 : Normal device operation
1 : Reset ADC and all registers

7.1.2 Register 01h (offset = 1h) [reset = 0h]

Figure 7-4 Register 01h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED DAISY_CHAIN_LEN RESERVED
R/W-0h R/W-0h R/W-0h
Figure 7-5 Register 01h Field Descriptions
Bit Field Type Reset Description
15-7 RESERVED R/W 0h Reserved. Do not change from the default reset value.
6-2 DAISY_CHAIN_LEN R/W 0h Configure the number of ADCs connected in daisy-chain for the SPI configuration.
0 : 1 ADC
1 : 2 ADCs
31 : 32 ADCs
1-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.1.3 Register 03h (offset = 3h) [reset = 2h]

Figure 7-6 Register 03h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
REG_BANK_SEL
R/W-2h
Figure 7-7 Register 03h Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7-0 REG_BANK_SEL R/W 2h Register bank selection for read and write operations.
0 : Select register bank 0
2 : Select register bank 1
16 : Select register bank 2

7.1.4 Register 04h (offset = 4h) [reset = 0h]

Figure 7-8 Register 04h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INIT_1
R/W-0h
Figure 7-9 Register 04h Field Descriptions
Bit Field Type Reset Description
3-0 INIT_1 R/W 0h INIT_1 field for device initialization. Write 1011b during the initialization sequence. Write 0000b for normal operation.

7.1.5 Register 06h (offset = 6h) [reset = 2h]

Figure 7-10 Register 06h
15 14 13 12 11 10 9 8
REG_00H_READBACK
R-0h
7 6 5 4 3 2 1 0
REG_00H_READBACK
R-5h
Figure 7-11 Register 06h Field Descriptions
Bit Field Type Reset Description
15-0 REG_00H_READBACK R 2h This register is a copy of the register address 0x00 for readback. The register address 0x00 is write-only. The default readback value is 2h because SPI_RD_EN in address 0x00 must be set to 1 for register reads.