ZHCSKW8C February   2020  – September 2023 ADS7066

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
      2. 7.3.2  Reference
        1. 7.3.2.1 External Reference
        2. 7.3.2.2 Internal Reference
      3. 7.3.3  ADC Transfer Function
      4. 7.3.4  ADC Offset Calibration
      5. 7.3.5  Programmable Averaging Filters
      6. 7.3.6  CRC on Data Interface
      7. 7.3.7  Oscillator and Timing Control
      8. 7.3.8  Diagnostic Modes
        1. 7.3.8.1 Bit-Walk Test Mode
        2. 7.3.8.2 Fixed Voltage Test Mode
      9. 7.3.9  Output Data Format
        1. 7.3.9.1 Status Flags
        2. 7.3.9.2 Output CRC (Device to Host)
        3. 7.3.9.3 Input CRC (Host to Device)
      10. 7.3.10 Device Programming
        1. 7.3.10.1 Enhanced-SPI Interface
        2. 7.3.10.2 Daisy-Chain Mode
        3. 7.3.10.3 Register Read/Write Operation
          1. 7.3.10.3.1 Register Write
          2. 7.3.10.3.2 Register Read
            1. 7.3.10.3.2.1 Register Read With CRC
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power-Up and Reset
      2. 7.4.2 Manual Mode
      3. 7.4.3 On-the-Fly Mode
      4. 7.4.4 Auto-Sequence Mode
    5. 7.5 ADS7066 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Charge-Kickback Filter and ADC Amplifier
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD and DVDD Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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7.3.6 CRC on Data Interface

The cyclic redundancy check (CRC) is an error checking code that detects communication errors to and from the host. CRC is the division remainder of the data payload bytes by a fixed polynomial. The data payload is two or three bytes, depending on the output data format; see the Output Data Format section for details on output data format. The CRC mode is optional and is enabled by the CRC_EN bit in the GENERAL_CFG register.

The CRC data byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) operation of the argument by a CRC polynomial. The CRC polynomial is based on the CRC-8-CCITT: X8 + X2 + X1 + 1. The nine binary polynomial coefficients are: 100000111. The CRC calculation is preset with 1 data values. For more details about the CRC implementation and for a software example, see the Implementation of CRC for ADS7066 application report.

The host must compute and append the appropriate CRC to the command string in the same SPI frame (see the Register Read/Write Operation section). The ADC also computes the expected CRC corresponding to the payload received from the host and compares the calculated CRC code to the CRC received from the host. The CRC received from the host and the CRC calculated by the ADC over the received payload are compared to check for an exact match.

  • If the calculated CRC and received CRC match then the data payload received from the host is valid.
  • If the calculated CRC and received CRC do not match then the data payload received from the host is not valid and the command does not execute. The CRCERR_IN flag is set to 1b. ADC conversion data read and register read processes, with a valid CRC from the host, are still supported. The error condition can be detected, as listed in Table 7-2, by either status flags or by a register read. Further register writes to the device are blocked until the CRCERR_IN flag is cleared to 0b. Register write operations, with a valid CRC from the host, to the SYSTEM_STATUS (address = 0x00) and GENERAL_CFG (address = 0x01) registers are still supported.

Table 7-2 Configuring Notifications When a CRC Error is Detected
CRC ERROR NOTIFICATION CONFIGURATION DESCRIPTION
Status flags APPEND_STATUS = 10b 4-bit status flags, containing the CRCERR_IN bit appended to the ADC data; see the Output Data Format section for details.
Register read — Read the CRCERR_IN bit to check if a CRC error was detected.

For a conversion data read or register data read, the ADC responds with a CRC that is computed over the requested data payload bytes. The response data payload is one, two, or three bytes depending on the data operation (see the Output CRC (Device to Host) section).