ZHCSKW8C February   2020  – September 2023 ADS7066

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
      2. 7.3.2  Reference
        1. 7.3.2.1 External Reference
        2. 7.3.2.2 Internal Reference
      3. 7.3.3  ADC Transfer Function
      4. 7.3.4  ADC Offset Calibration
      5. 7.3.5  Programmable Averaging Filters
      6. 7.3.6  CRC on Data Interface
      7. 7.3.7  Oscillator and Timing Control
      8. 7.3.8  Diagnostic Modes
        1. 7.3.8.1 Bit-Walk Test Mode
        2. 7.3.8.2 Fixed Voltage Test Mode
      9. 7.3.9  Output Data Format
        1. 7.3.9.1 Status Flags
        2. 7.3.9.2 Output CRC (Device to Host)
        3. 7.3.9.3 Input CRC (Host to Device)
      10. 7.3.10 Device Programming
        1. 7.3.10.1 Enhanced-SPI Interface
        2. 7.3.10.2 Daisy-Chain Mode
        3. 7.3.10.3 Register Read/Write Operation
          1. 7.3.10.3.1 Register Write
          2. 7.3.10.3.2 Register Read
            1. 7.3.10.3.2.1 Register Read With CRC
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power-Up and Reset
      2. 7.4.2 Manual Mode
      3. 7.4.3 On-the-Fly Mode
      4. 7.4.4 Auto-Sequence Mode
    5. 7.5 ADS7066 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Charge-Kickback Filter and ADC Amplifier
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD and DVDD Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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7.3.10.2 Daisy-Chain Mode

The ADS7066 can operate as a single converter or in a system with multiple converters. System designers can take advantage of the simple, high-speed, enhanced-SPI serial interface by cascading converters in a daisy-chain configuration when multiple converters are used. No register configuration is required to enable daisy-chain mode. Figure 7-7 shows a typical connection of three converters in daisy-chain mode.

GUID-BF3603E2-1C29-453D-981D-A1F2B1FF5E79-low.gif Figure 7-7 Multiple Converters Connected Using Daisy-Chain Mode

When the ADS7066 is connected in daisy-chain mode, the serial input data passes through the ADS7066 with a 24-SCLK delay, as long as CS is active. Figure 7-8 shows a detailed timing diagram of this mode. In Figure 7-8, the conversion in each converter is performed simultaneously.

GUID-511A20DD-45FC-4812-91C4-3D4FBFE57611-low.gif Figure 7-8 Simplified Daisy-Chain Mode Timing

The ADS7066 supports daisy-chain mode for output data payloads up to 24 bits long; see the Output Data FormatOutput Data Format section for more details. If either the status flags or channel ID are appended (APPEND_STATUS ≠ 00b) and the CRC module is enabled (CRC_EN = 1b), then the serial input data does not pass through the ADS7066 and daisy-chain mode is disabled.