SLWS214C October   2008  – May 2026 ADS61B29 , ADS61B49

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Configuration and Functions (LVDS Mode) — ADS61B49 and ADS61B29
    2. 4.2 Pin Configuration and Functions (CMOS Mode) – ADS61B49 and ADS61B29
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions
    3. 5.3  Electrical Characteristics – ADS61B49 and ADS61B29
    4. 5.4  Electrical Characteristics – ADS61B49 and ADS61B29
    5. 5.5  Electrical Characteristics – ADS61B49 and ADS61B29
    6. 5.6  Digital Characteristics – ADS61B49 and ADS61B29
    7. 5.7  Timing Requirements – LVDS and CMOS Modes
    8. 5.8  Typical Characteristics - ADS61B49
    9. 5.9  Typical Characteristics - ADS61B29
    10. 5.10 Typical Characteristics - Common Plots (both ADS61B49/61B29)
    11. 5.11 Contour Plots - ADS61B49/ADS61B29
    12. 5.12 Contour Plots - ADS61B49
    13. 5.13 Contour Plots - ADS61B29
  7. 6 Detailed Description
    1. 6.1 Functional Block Diagrams
      1. 6.1.1 ADS61B29 Block Diagram
      2. 6.1.2 ADS61B49 Block Diagram
    2. 6.2 Feature Description
      1. 6.2.1 Device Configuration
      2. 6.2.2 Parallel Configuration Only
      3. 6.2.3 Serial Interface Configuration Only
      4. 6.2.4 Configuration Using Both The Serial Interface and Parallel Controls
      5. 6.2.5 Description of Parallel Pins
      6. 6.2.6 Serial Interface
        1. 6.2.6.1 Register Initialization
      7. 6.2.7 Serial Interface Timing Characteristics
      8. 6.2.8 Serial Register Readout
      9. 6.2.9 Reset Timing
    3. 6.3 Serial Register Map
      1. 6.3.1 Description of Serial Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Theory of Operation
      2. 7.1.2  Analog Input
        1. 7.1.2.1 Drive Circuit Requirements
        2. 7.1.2.2 Driving Circuit
        3. 7.1.2.3 Input Common-Mode
      3. 7.1.3  Reference
      4. 7.1.4  Clock Input
      5. 7.1.5  Fine Gain Control
      6. 7.1.6  Offset Correction
      7. 7.1.7  Power Down
        1. 7.1.7.1 Power-Down Global
        2. 7.1.7.2 Standby
        3. 7.1.7.3 Output Buffer Disable
        4. 7.1.7.4 Input Clock Stop
      8. 7.1.8  Power Supply Sequence
      9. 7.1.9  Digital Output Information
        1. 7.1.9.1 Output Interface
        2. 7.1.9.2 DDR LVDS Outputs
        3. 7.1.9.3 LVDS Buffer
        4. 7.1.9.4 Parallel CMOS Interface
        5. 7.1.9.5 Output Buffer Strength Programmability
        6. 7.1.9.6 CMOS Interface Power Dissipation
        7. 7.1.9.7 Output Data Format
      10. 7.1.10 Board Design Considerations
        1. 7.1.10.1 Grounding
        2. 7.1.10.2 Supply Decoupling
        3. 7.1.10.3 Exposed Pad
      11. 7.1.11 Definition of Specifications
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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5.7 Timing Requirements – LVDS and CMOS Modes

Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock,
CLOAD = 5 pF(2), RLOAD = 100 Ω(3), Low Speed mode disabled, unless otherwise noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.7 V to 1.9 V.(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
taAperture delay0.71.21.7ns
tjAperture jitter170fs rms
Wake-up timeTime to valid data after coming out of STANDBY mode0.31μs
Time to valid data after coming out of PDN GLOBAL mode25100
Time to valid data after stopping and restarting the input clock10Clock Cycles
ADC Latency(8)Default, after reset18Clock Cycles
DDR LVDS MODE (4)
tsuData setup timeData valid (5) to zero-crossing of CLKOUTP0.81.2ns
thData hold timeZero-crossing of CLKOUT to data becoming invalid(5)0.250.6ns
tPDIClock propagation delayInput clock rising edge cross-over to output clock rising edge cross-over
80MSPS ≤ Sampling frequency ≤ 250MSPS		0.2 × ts + tdelayns
tdelay56.27.5ns
LVDS bit clock duty cycleDuty cycle of differential clock, (CLKOUTP–CLKOUTM)
80MSPS ≤ Sampling frequency ≤ 250MSPS		52%
tRISE,
tFALL		Data rise time,
Data fall time		Rise time measured from –100mV to 100mV
Fall time measured from 100mV to –100mV
1MSPS ≤ Sampling frequency ≤ 250MSPS		0.080.140.2ns
tCLKRISE,
tCLKFALL		Output clock rise time,
Output clock fall time		Rise time measured from –100mV to 100mV
Fall time measured from 100mV to –100mV
1MSPS ≤ Sampling frequency ≤ 250MSPS		0.080.140.2ns
tOEOutput enable (OE) to data delayTime to valid data after OE becomes active40ns
PARALLEL CMOS MODE(7)
tSTARTInput clock to data delayInput clock rising edge cross-over to start of data valid(6)3.2ns
tDVData valid timeTime interval of valid data(6)0.71.5ns
tPDIClock propagation delayInput clock rising edge cross-over to output clock rising edge cross-over
80MSPS ≤ Sampling frequency ≤ 150MSPS		0.78 × ts + tdelayns
tdelay56.58ns
Output clock duty cycleDuty cycle of differential clock, (CLKOUT)
80MSPS ≤ Sampling frequency ≤ 150MSPS		50%
tRISE,
tFALL		Data rise time,
Data fall time		Rise time measured from 20% to 80% of DRVDD,
Fall time measured from 80% to 20% of DRVDD,
1MSPS ≤ Sampling frequency ≤ 250MSPS		0.71.22ns
tCLKRISE,
tCLKFALL		Output clock rise time,
Output clock fall time		Rise time measured from 20% to 80% of DRVDD,
Fall time measured from 80% to 20% of DRVDD,
1MSPS ≤ Sampling frequency ≤ 150MSPS		0.511.5ns
tOEOutput enable (OE) to data delayTime to valid data after OE becomes active20ns
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to logic high of +100mV and logic low of –100mV.
(6) Data valid refers to logic high of 1.26V and logic low of 0.54V.
(7) For Fs > 150MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT).
(8) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Table 5-1 LVDS Timings at Lower Sampling Frequencies
SAMPLING FREQUENCY, MSPSSETUP TIME, nsHOLD TIME, ns
MINTYPMAXMINTYPMAX
2101.01.40.40.8
1901.11.50.50.9
1701.31.70.71.1
1501.61.90.91.2
1251.92.21.11.4
<80
Enable low speed mode		2.52.0
tPDI, ns
MINTYPMAX
1 ≤ Fs ≤ 80,
Enable low speed mode		8.2
Table 5-2 CMOS Timings at Lower Sampling Frequencies
SAMPLING FREQUENCY, MSPSTIMINGS SPECIFIED WITH RESPECT TO INPUT CLOCK
tSTART, nsDATA VALID TIME, ns
MINTYPMAXMINTYPMAX
2101.71.62.4
1900.42.23.0
1705.12.43.6
1504.83.04.3
SAMPLING FREQUENCY, MSPSTIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SETUP TIME, nsHOLD TIME, ns
MINTYPMAXMINTYPMAX
1502.03.21.52.2
1252.942.22.7
<80
Enable low speed mode		5.03.8
tPDI, ns
MINTYPMAX
1 ≤ Fs ≤ 80,
Enable low speed mode		14
ADS61B29 ADS61B49 Latency DiagramFigure 5-2 Latency Diagram
ADS61B29 ADS61B49 LVDS Mode TimingFigure 5-3 LVDS Mode Timing
ADS61B29 ADS61B49 CMOS Mode TimingFigure 5-4 CMOS Mode Timing