ZHCSFU8B May 2016 – December 2021 ADC32RF80 , ADC32RF83
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | DIG CORE RESET GBL |
| W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | 0 | W | 0h | Must write 0 |
| 0 | DIG CORE RESET GBL | R/W | 0h | Pulse this bit (0 →1 →0) to reset the digital core (applies to both channel A and B). All Nyquist zone settings take effect when this bit is pulsed. |