ZHCSFU8B May 2016 – December 2021 ADC32RF80 , ADC32RF83
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | DDC DET LAT | 0 | 0 | 0 | 0 | ||
| W-0h | R/W-5h | W-1h | W-1h | W-1h | W-1h | ||
| Bit | Field | Type | Reset | Description | |
|---|---|---|---|---|---|
| 7 | 0 | W | 0h | Must write 0 | |
| 6-4 | DDC DET LAT | R/W | 5h | These bits ensure deterministic latency depending on the decimation setting used; see Table 8-91. | |
| 3-0 | 0 | W | 1h | Must write 0 | |
| SETTING | COMPLEX DECIMATION SETTING |
|---|---|
| 10h | Divide-by-24, -32 complex |
| 20h | Divide-by-16, -18, -20 complex |
| 40h | Divide-by-by 6, -12 complex |
| 50h | Divide-by-4, -8, -9, -10 complex |