ZHCSUL6 February 2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500
PRODUCTION DATA
The ADC12DLx500 clock inputs must be AC-coupled to the device for rated performance. The clock source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended clock synthesizers include the LMX2594, LMX2592, and LMX2582.
For multi-device synchronization or deterministic latency the data converter system (ADC plus FPGA) requires a SYSREF signal in addition to the device (sampling) clock, which is similar to that used for JESD204B converters. Therefore, JESD204B compatible clock devices are a good choice for clocking the ADC12DLx500. The LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on the ADC clock frequency and jitter requirements, this device can also be used as the system clock synthesizer or as a device clock and SYSREF distribution device when multiple ADC12DLx500 devices are used in a system.