SPRUJ53 April 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 17-7 lists the memory-mapped registers for the PGA_REGS registers. All register offset addresses not listed in Table 17-7 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | PGACTL | PGA Control Register | EALLOW,LOCK: PGALOCK_TYPE2.PGACTL | Go |
1h | MUXSEL | Mux Selection Register | EALLOW,LOCK: PGALOCK_TYPE2.MUXSEL | Go |
2h | OFFSETTRIM | Offset Trim Register | EALLOW,LOCK: PGALOCK_TYPE2.OFFSETTRIM | Go |
5h | PGATYPE | PGA Type Register | Go | |
6h | PGALOCK | PGA Lock Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 17-8 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value |
PGACTL is shown in Figure 17-19 and described in Table 17-9.
Return to the Summary Table.
PGA Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CHOP_EXTCTRL | RESERVED | PGA_OUTEN_INTGAIN | PGA_OUTENABLE | ||||
R/W-0h | R-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GAIN | RESERVED | FILT_RES_SEL | PGAEN | ||||
R/W-0h | R-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | CHOP_EXTCTRL | R/W | 0h | CHOP Signal Control 0 Chop signal is low 1 Chop signal is high Reset type: SYSRSn |
14-10 | RESERVED | R | 0h | Reserved |
9 | PGA_OUTEN_INTGAIN | R/W | 0h | PGA Internal Gain on Pin 0 PGA internal gain path comes to a pin 1 PGA nternal gain path does not come to a pin Reset type: SYSRSn |
8 | PGA_OUTENABLE | R/W | 0h | PGA Output Enable 0 PGA Output does not come to a pin 1 PGA Output does come to a pin Reset type: SYSRSn |
7-5 | GAIN | R/W | 0h | PGA Gain programming-1-64 000 x 1 001 x 2/-1 010 x 4/-3 011 x 8/-7 100 x 16/-15 101 x 32/-31 110 x 64/-63 111 reserved Reset type: SYSRSn |
4 | RESERVED | R | 0h | Reserved |
3-1 | FILT_RES_SEL | R/W | 0h | Filter Resistor Select 000 Filter Disabled 001 50 010 100 011 200 100 400 101 800 110 Filter Disabled 111 Filter Disabled Reset type: SYSRSn |
0 | PGAEN | R/W | 0h | PGA Enable. 0 PGA is disabled and powered down. 1 PGA is enabled. Reset type: SYSRSn |
MUXSEL is shown in Figure 17-20 and described in Table 17-10.
Return to the Summary Table.
Mux Selection Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PGA_CHOP | PGA_FBONPIN | RESERVED | MMUXSEL | |||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NMUXSEL | RESERVED | PMUXSEL | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14-13 | PGA_CHOP | R/W | 0h | PGA Output Chopping Control 00 Chopping Disabled 01 Reserved 10 ADC assisted chop (using ADCSOC as ctrl) 11 ADC assisted chop (using PGA_CHOP_EXTCTRL register0 Reset type: SYSRSn |
12 | PGA_FBONPIN | R/W | 0h | PGA Feedback to Negative Input Connection 0 PGA_INM and Inverting Input are not connected 1 PGA_INM and Inverting Input are connected Reset type: SYSRSn |
11-10 | RESERVED | R | 0h | Reserved |
9-8 | MMUXSEL | R/W | 0h | PGA M Mux Select 00 Naked op-amp or G=1 mode select 01 Non-Inverting gain mode Select, feeback resistors have path to VSSA 10 Inverting gain mode Select, feedback resistors have path to Iocal PGA_INM pin 11 Inverterting Gain Mode Select, feedback resistors have path to PGA_INM_SHARED pin Reset type: SYSRSn |
7-6 | RESERVED | R | 0h | Reserved |
5-4 | NMUXSEL | R/W | 0h | PGA Negative Input Mux Select 00 Select RTOP(Inter Gain Resistor Tap Point) as inverting input 01 Select RTAP(Pre Gain Resistor Tap Point) as inverting input 10 Select PGA_INM pin as inverting input 11 Reserved Reset type: SYSRSn |
3-2 | RESERVED | R | 0h | Reserved |
1-0 | PMUXSEL | R/W | 0h | PGA Positive Input Mux Select 00 Select PGA_INP pin as non inverting input 01 Select VSSA as non-inverting input 10 Reserved 11 Reserved Reset type: SYSRSn |
OFFSETTRIM is shown in Figure 17-21 and described in Table 17-11.
Return to the Summary Table.
Offset Trim Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PGA_OFFSETTRIMP | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PGA_OFFSETTRIMN | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | PGA_OFFSETTRIMP | R/W | 0h | PGA internal (analog) offset trim feature for i/p PMOS pair Reset type: SYSRSn |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | PGA_OFFSETTRIMN | R/W | 0h | PGA internal (analog) offset trim feature for i/p NMOS pair Reset type: SYSRSn |
PGATYPE is shown in Figure 17-22 and described in Table 17-12.
Return to the Summary Table.
PGA Type Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TYPE | |||||||
R-2h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TYPE | R | 2h | PGA Type. Reset type: SYSRSn |
7-0 | REV | R | 0h | PGA Revision. Reset type: SYSRSn |
PGALOCK is shown in Figure 17-23 and described in Table 17-13.
Return to the Summary Table.
PGA Lock Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | PGATMCTL | OFFSETTRIM | MUXSEL | PGACTL |
WSonce-0h | R-0h | R-0h | R-0h | WSonce-0h | WSonce-0h | WSonce-0h | WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | WSonce | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | PGATMCTL | WSonce | 0h | 0 Writes to PGATMCTL are enabled. 1 Writes to PGATMCTL are disabled. Reset type: SYSRSn |
2 | OFFSETTRIM | WSonce | 0h | 0 Writes to OFFSETTRIM are enabled. 1 Writes to OFFSETTRIM are disabled. Reset type: SYSRSn |
1 | MUXSEL | WSonce | 0h | 0 Writes to MUXSEL are enabled. 1 Writes to MUXSEL are disabled. Reset type: SYSRSn |
0 | PGACTL | WSonce | 0h | 0 Writes to PGACTL are enabled. 1 Writes to PGACTL are disabled. Reset type: SYSRSn |