SPRUJ53A
April 2024 – June 2024
TMS320F28P550SJ
,
TMS320F28P559SJ-Q1
1
Read This First
About This Manual
Notational Conventions
Glossary
Related Documentation From Texas Instruments
Support Resources
Trademarks
1
C2000™ Microcontrollers Software Support
1.1
Introduction
1.2
C2000Ware Structure
1.3
Documentation
1.4
Devices
1.5
Libraries
1.6
Code Composer Studio™ Integrated Development Environment (IDE)
1.7
SysConfig and PinMUX Tool
2
C28x Processor
2.1
Introduction
2.2
C28X Related Collateral
2.3
Features
2.4
Floating-Point Unit
2.5
Trigonometric Math Unit (TMU)
2.6
VCRC Unit
3
System Control and Interrupts
3.1
Introduction
3.1.1
SYSCTL Related Collateral
3.1.2
LOCK Protection on System Configuration Registers
3.1.3
EALLOW Protection
3.2
Power Management
3.3
Device Identification and Configuration Registers
3.4
Resets
3.4.1
Reset Sources
3.4.2
External Reset (XRS)
3.4.3
Simulate External Reset (SIMRESET. XRS)
3.4.4
Power-On Reset (POR)
3.4.5
Brown-Out Reset (BOR)
3.4.6
Debugger Reset (SYSRS)
3.4.7
Simulate CPU Reset
3.4.8
Watchdog Reset (WDRS)
3.4.9
NMI Watchdog Reset (NMIWDRS)
3.4.10
DCSM Safe Code Copy Reset (SCCRESET)
3.5
Peripheral Interrupts
3.5.1
Interrupt Concepts
3.5.2
Interrupt Architecture
3.5.2.1
Peripheral Stage
3.5.2.2
PIE Stage
3.5.2.3
CPU Stage
3.5.3
Interrupt Entry Sequence
3.5.4
Configuring and Using Interrupts
3.5.4.1
Enabling Interrupts
3.5.4.2
Handling Interrupts
3.5.4.3
Disabling Interrupts
3.5.4.4
Nesting Interrupts
3.5.4.5
Vector Address Validity Check
3.5.5
PIE Channel Mapping
3.5.6
PIE Interrupt Priority
3.5.6.1
Channel Priority
3.5.6.2
Group Priority
3.5.7
System Error
3.5.8
Vector Tables
3.6
Exceptions and Non-Maskable Interrupts
3.6.1
Configuring and Using NMIs
3.6.2
Emulation Considerations
3.6.3
NMI Sources
3.6.3.1
Missing Clock Detection
3.6.3.2
RAM Uncorrectable Error
3.6.3.3
Flash Uncorrectable ECC Error
3.6.3.4
Software-Forced Error
3.6.3.5
ERAD NMI
3.6.4
Illegal Instruction Trap (ITRAP)
3.6.5
ERRORSTS Pin
3.7
Clocking
3.7.1
Clock Sources
3.7.1.1
Primary Internal Oscillator (INTOSC2)
3.7.1.2
Backup Internal Oscillator (INTOSC1)
3.7.1.3
Auxiliary Clock Input (AUXCLKIN)
3.7.1.4
External Oscillator (XTAL)
3.7.2
Derived Clocks
3.7.2.1
Oscillator Clock (OSCCLK)
3.7.2.2
System PLL Output Clock (PLLRAWCLK)
3.7.3
Device Clock Domains
3.7.3.1
System Clock (PLLSYSCLK)
3.7.3.2
CPU Clock (CPUCLK)
3.7.3.3
CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
3.7.3.4
Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
3.7.3.5
USB Bit Clock
3.7.3.6
CAN Bit Clock
3.7.3.7
CLB Clock
3.7.3.8
LIN Clock
3.7.3.9
CPU Timer2 Clock (TIMER2CLK)
3.7.4
XCLKOUT
3.7.5
Clock Connectivity
3.7.6
Clock Source and PLL Setup
3.7.7
Using an External Crystal or Resonator
3.7.7.1
X1/X2 Precondition Circuit
3.7.8
Using an External Oscillator
3.7.9
Choosing PLL Settings
3.7.10
System Clock Setup
3.7.11
SYS PLL Bypass
3.7.12
Clock (OSCCLK) Failure Detection
3.7.12.1
Missing Clock Detection
3.8
32-Bit CPU Timers 0/1/2
3.9
Watchdog Timer
3.9.1
Servicing the Watchdog Timer
3.9.2
Minimum Window Check
3.9.3
Watchdog Reset or Watchdog Interrupt Mode
3.9.4
Watchdog Operation in Low-Power Modes
3.9.5
Emulation Considerations
3.10
Low-Power Modes
3.10.1
Clock-Gating Low-Power Modes
3.10.2
IDLE
3.10.3
STANDBY
3.10.4
HALT
3.11
Memory Controller Module
3.11.1
Functional Description
3.11.1.1
Dedicated RAM (Mx RAM)
3.11.1.2
Local Shared RAM (LSx RAM)
3.11.1.3
Global Shared RAM (GSx RAM)
3.11.1.4
CAN Message RAM
3.11.1.5
CLA-CPU Message RAM
3.11.1.6
CLA-DMA Message RAM
3.11.1.7
Access Arbitration
3.11.1.8
Access Protection
3.11.1.8.1
CPU Fetch Protection
3.11.1.8.2
CPU Write Protection
3.11.1.8.3
CPU Read Protection
3.11.1.8.4
CLA Fetch Protection
3.11.1.8.5
CLA Write Protection
3.11.1.8.6
CLA Read Protection
3.11.1.8.7
DMA Write Protection
3.11.1.8.8
NPU Write Protection
3.11.1.9
Memory Error Detection, Correction, and Error Handling
3.11.1.9.1
Error Detection and Correction
3.11.1.9.2
Error Handling
3.11.1.10
Application Test Hooks for Error Detection and Correction
3.11.1.11
RAM Initialization
3.12
JTAG
3.12.1
JTAG Noise and TAP_STATUS
3.13
Live Firmware Update
3.13.1
LFU Background
3.13.2
LFU Switchover Steps
3.13.3
Device Features Supporting LFU
3.13.3.1
Multi-Bank Flash
3.13.3.2
PIE Vector Table Swap
3.13.3.3
LS0/LS1 RAM Memory Swap
3.13.3.3.1
Applicability to CLA LFU
3.13.4
LFU Switchover
3.13.5
LFU Resources
3.14
System Control Register Configuration Restrictions
3.15
Software
3.15.1
SYSCTL Registers to Driverlib Functions
3.15.2
CPUTIMER Registers to Driverlib Functions
3.15.3
MEMCFG Registers to Driverlib Functions
3.15.4
PIE Registers to Driverlib Functions
3.15.5
NMI Registers to Driverlib Functions
3.15.6
XINT Registers to Driverlib Functions
3.15.7
WWD Registers to Driverlib Functions
3.15.8
SYSCTL Examples
3.15.8.1
Missing clock detection (MCD)
3.15.8.2
XCLKOUT (External Clock Output) Configuration
3.15.9
TIMER Examples
3.15.9.1
CPU Timers
3.15.9.2
CPU Timers
3.15.10
MEMCFG Examples
3.15.10.1
Correctable & Uncorrectable Memory Error Handling
3.15.11
INTERRUPT Examples
3.15.11.1
External Interrupts (ExternalInterrupt)
3.15.11.2
Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
3.15.11.3
CPU Timer Interrupt Software Prioritization
3.15.11.4
EPWM Real-Time Interrupt
3.15.12
LPM Examples
3.15.12.1
Low Power Modes: Device Idle Mode and Wakeup using GPIO
3.15.12.2
Low Power Modes: Device Idle Mode and Wakeup using Watchdog
3.15.12.3
Low Power Modes: Device Standby Mode and Wakeup using GPIO
3.15.12.4
Low Power Modes: Device Standby Mode and Wakeup using Watchdog
3.15.12.5
Low Power Modes: Halt Mode and Wakeup using GPIO
3.15.12.6
Low Power Modes: Halt Mode and Wakeup
3.15.13
WATCHDOG Examples
3.15.13.1
Watchdog
3.16
SYSCTRL Registers
3.16.1
SYSCTRL Base Address Table
3.16.2
CPUTIMER_REGS Registers
3.16.3
PIE_CTRL_REGS Registers
3.16.4
NMI_INTRUPT_REGS Registers
3.16.5
XINT_REGS Registers
3.16.6
SYNC_SOC_REGS Registers
3.16.7
DMA_CLA_SRC_SEL_REGS Registers
3.16.8
LFU_REGS Registers
3.16.9
DEV_CFG_REGS Registers
3.16.10
CLK_CFG_REGS Registers
3.16.11
CPU_SYS_REGS Registers
3.16.12
SYS_STATUS_REGS Registers
3.16.13
PERIPH_AC_REGS Registers
3.16.14
MEM_CFG_REGS Registers
3.16.15
ACCESS_PROTECTION_REGS Registers
3.16.16
MEMORY_ERROR_REGS Registers
3.16.17
TEST_ERROR_REGS Registers
3.16.18
UID_REGS Registers
4
ROM Code and Peripheral Booting
4.1
Introduction
4.1.1
ROM Related Collateral
4.2
Device Boot Sequence
4.3
Device Boot Modes
4.3.1
Default Boot Modes
4.3.2
Custom Boot Modes
4.4
Device Boot Configurations
4.4.1
Configuring Boot Mode Pins
4.4.2
Configuring Boot Mode Table Options
4.4.3
Boot Mode Example Use Cases
4.4.3.1
Zero Boot Mode Select Pins
4.4.3.2
One Boot Mode Select Pin
4.4.3.3
Three Boot Mode Select Pins
4.5
Device Boot Flow Diagrams
4.5.1
Boot Flow
4.5.2
Emulation Boot Flow
4.5.3
Standalone Boot Flow
4.6
Device Reset and Exception Handling
4.6.1
Reset Causes and Handling
4.6.2
Exceptions and Interrupts Handling
4.7
Boot ROM Description
4.7.1
Boot ROM Configuration Registers
4.7.1.1
MPOST Configuration
4.7.2
Entry Points
4.7.3
Wait Points
4.7.4
Secure Flash Boot
4.7.4.1
Secure Flash CPU1 Linker File Example
4.7.5
Firmware Update (FWU) Flash Boot
4.7.6
Memory Maps
4.7.6.1
Boot ROM Memory Maps
4.7.6.2
CLA Data ROM Memory Maps
4.7.6.3
Reserved RAM Memory Maps
4.7.7
ROM Tables
4.7.8
Boot Modes and Loaders
4.7.8.1
Boot Modes
4.7.8.1.1
Flash Boot
4.7.8.1.2
RAM Boot
4.7.8.1.3
Wait Boot
4.7.8.2
Bootloaders
4.7.8.2.1
SCI Boot Mode
4.7.8.2.2
SPI Boot Mode
4.7.8.2.3
I2C Boot Mode
4.7.8.2.4
Parallel Boot Mode
4.7.8.2.5
CAN Boot Mode (MCAN in non-FD mode)
4.7.8.2.6
CAN-FD Boot Mode
4.7.8.2.7
USB Boot Mode
4.7.9
GPIO Assignments
4.7.10
Secure ROM Function APIs
4.7.11
Clock Initializations
4.7.12
Boot Status Information
4.7.12.1
Booting Status
4.7.12.2
Boot Mode and MPOST (Memory Power On Self-Test) Status
4.7.13
ROM Version
4.8
Application Notes for Using the Bootloaders
4.8.1
Bootloader Data Stream Structure
4.8.1.1
Data Stream Structure 8-bit
4.8.2
The C2000 Hex Utility
4.8.2.1
HEX2000.exe Command Syntax
4.9
Software
4.9.1
BOOT Examples
5
Dual Code Security Module (DCSM)
5.1
Introduction
5.1.1
DCSM Related Collateral
5.2
Functional Description
5.2.1
CSM Passwords
5.2.2
Emulation Code Security Logic (ECSL)
5.2.3
CPU Secure Logic
5.2.4
Execute-Only Protection
5.2.5
Password Lock
5.2.6
JTAGLOCK
5.2.7
Link Pointer and Zone Select
5.2.8
C Code Example to Get Zone Select Block Addr for Zone1
5.3
Flash and OTP Erase/Program
5.4
Secure Copy Code
5.5
SecureCRC
5.6
CSM Impact on Other On-Chip Resources
5.7
Incorporating Code Security in User Applications
5.7.1
Environments That Require Security Unlocking
5.7.2
CSM Password Match Flow
5.7.3
C Code Example to Unsecure C28x Zone1
5.7.4
C Code Example to Resecure C28x Zone1
5.7.5
Environments That Require ECSL Unlocking
5.7.6
ECSL Password Match Flow
5.7.7
ECSL Disable Considerations for any Zone
5.7.7.1
C Code Example to Disable ECSL for C28x Zone1
5.7.8
Device Unique ID
5.8
Software
5.8.1
DCSM Registers to Driverlib Functions
5.8.2
DCSM Examples
5.8.2.1
Empty DCSM Tool Example
5.9
DCSM Registers
5.9.1
DCSM Base Address Table
5.9.2
DCSM_Z1_REGS Registers
5.9.3
DCSM_Z2_REGS Registers
5.9.4
DCSM_COMMON_REGS Registers
5.9.5
DCSM_Z1_OTP Registers
5.9.6
DCSM_Z2_OTP Registers
6
Flash Module
6.1
Introduction to Flash and OTP Memory
6.1.1
FLASH Related Collateral
6.1.2
Features
6.1.3
Flash Tools
6.1.4
Default Flash Configuration
6.2
Flash Bank, OTP, and Pump
6.3
Flash Wrapper
6.4
Flash and OTP Memory Performance
6.5
Flash Read Interface
6.5.1
C28x-Flash Read Interface
6.5.1.1
Standard Read Mode
6.5.1.2
Prefetch Mode
6.5.1.3
Data Cache
6.5.1.4
Flash Read Operation
6.6
Flash Erase and Program
6.6.1
Erase
6.6.2
Program
6.6.3
Verify
6.7
Error Correction Code (ECC) Protection
6.7.1
Single-Bit Data Error
6.7.2
Uncorrectable Error
6.7.3
Mechanism to Check the Correctness of ECC Logic
6.8
Reserved Locations Within Flash and OTP
6.9
Migrating an Application from RAM to Flash
6.10
Procedure to Change the Flash Control Registers
6.11
Software
6.11.1
FLASH Registers to Driverlib Functions
6.11.2
FLASH Examples
6.11.2.1
Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
6.11.2.2
Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
6.12
FLASH Registers
6.12.1
FLASH Base Address Table
6.12.2
FLASH_CTRL_REGS Registers
6.12.3
FLASH_ECC_REGS Registers
7
Control Law Accelerator (CLA)
7.1
Introduction
7.1.1
Features
7.1.2
CLA Related Collateral
7.1.3
Block Diagram
7.2
CLA Interface
7.2.1
CLA Memory
7.2.2
CLA Memory Bus
7.2.3
Shared Peripherals and EALLOW Protection
7.2.4
CLA Tasks and Interrupt Vectors
7.3
CLA, DMA, and CPU Arbitration
7.3.1
CLA Message RAM
7.3.2
CLA Program Memory
7.3.3
CLA Data Memory
7.3.4
Peripheral Registers (ePWM, HRPWM, Comparator)
7.4
CLA Configuration and Debug
7.4.1
Building a CLA Application
7.4.2
Typical CLA Initialization Sequence
7.4.3
Debugging CLA Code
7.4.3.1
Breakpoint Support (MDEBUGSTOP)
7.4.4
CLA Illegal Opcode Behavior
7.4.5
Resetting the CLA
7.5
Pipeline
7.5.1
Pipeline Overview
7.5.2
CLA Pipeline Alignment
7.5.2.1
Code Fragment For MBCNDD, MCCNDD, or MRCNDD
358
7.5.2.2
Code Fragment for Loading MAR0 or MAR1
360
7.5.2.3
ADC Early Interrupt to CLA Response
7.5.3
Parallel Instructions
7.5.3.1
Math Operation with Parallel Load
7.5.3.2
Multiply with Parallel Add
7.5.4
CLA Task Execution Latency
7.6
Software
7.6.1
CLA Registers to Driverlib Functions
7.6.2
CLA Examples
7.6.2.1
CLA arcsine(x) using a lookup table (cla_asin_cpu01)
7.6.2.2
CLA arcsine(x) using a lookup table (cla_asin_cpu01)
7.6.2.3
CLA arctangent(x) using a lookup table (cla_atan_cpu01)
7.6.2.4
CLA background nesting task
7.6.2.5
Controlling PWM output using CLA
7.6.2.6
Just-in-time ADC sampling with CLA
7.6.2.7
Optimal offloading of control algorithms to CLA
7.6.2.8
Handling shared resources across C28x and CLA
7.7
Instruction Set
7.7.1
Instruction Descriptions
7.7.2
Addressing Modes and Encoding
7.7.3
Instructions
MABSF32 MRa, MRb
MADD32 MRa, MRb, MRc
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MBCNDD 16BitDest [, CNDF]
MCCNDD 16BitDest [, CNDF]
MCMP32 MRa, MRb
MCMPF32 MRa, MRb
MCMPF32 MRa, #16FHi
MDEBUGSTOP
MEALLOW
MEDIS
MEINVF32 MRa, MRb
MEISQRTF32 MRa, MRb
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOI32 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MF32TOUI32 MRa, MRb
MFRACF32 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
MMAXF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi
MMOV16 MARx, MRa, #16I
MMOV16 MARx, mem16
MMOV16 mem16, MARx
MMOV16 mem16, MRa
MMOV32 mem32, MRa
MMOV32 mem32, MSTF
MMOV32 MRa, mem32 [, CNDF]
MMOV32 MRa, MRb [, CNDF]
MMOV32 MSTF, mem32
MMOVD32 MRa, mem32
MMOVF32 MRa, #32F
MMOVI16 MARx, #16I
MMOVI32 MRa, #32FHex
MMOVIZ MRa, #16FHi
MMOVZ16 MRa, mem16
MMOVXI MRa, #16FLoHex
MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, #16FHi
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
MNEGF32 MRa, MRb[, CNDF]
MNOP
MOR32 MRa, MRb, MRc
MRCNDD [CNDF]
MSETFLG FLAG, VALUE
MSTOP
MSUB32 MRa, MRb, MRc
MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
MSWAPF MRa, MRb [, CNDF]
MTESTTF CNDF
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
MUI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MXOR32 MRa, MRb, MRc
7.8
CLA Registers
7.8.1
CLA Base Address Table
7.8.2
CLA_ONLY_REGS Registers
7.8.3
CLA_SOFTINT_REGS Registers
7.8.4
CLA_REGS Registers
8
Dual-Clock Comparator (DCC)
8.1
Introduction
8.1.1
Features
8.1.2
Block Diagram
8.2
Module Operation
8.2.1
Configuring DCC Counters
8.2.2
Single-Shot Measurement Mode
8.2.3
Continuous Monitoring Mode
8.2.4
Error Conditions
8.3
Interrupts
8.4
Software
8.4.1
DCC Registers to Driverlib Functions
8.4.2
DCC Examples
8.4.2.1
DCC Single shot Clock verification
8.4.2.2
DCC Single shot Clock measurement
8.4.2.3
DCC Continuous clock monitoring
8.4.2.4
DCC Continuous clock monitoring
8.4.2.5
DCC Detection of clock failure
8.5
DCC Registers
8.5.1
DCC Base Address Table
8.5.2
DCC_REGS Registers
9
General-Purpose Input/Output (GPIO)
9.1
Introduction
9.1.1
GPIO Related Collateral
9.2
Configuration Overview
9.3
Digital Inputs on ADC Pins (AIOs)
9.4
Digital Inputs and Outputs on ADC Pins (AGPIOs)
9.5
Digital General-Purpose I/O Control
9.6
Input Qualification
9.6.1
No Synchronization (Asynchronous Input)
9.6.2
Synchronization to SYSCLKOUT Only
9.6.3
Qualification Using a Sampling Window
9.7
USB Signals
9.8
PMBUS and I2C Signals
9.9
GPIO and Peripheral Muxing
9.9.1
GPIO Muxing
9.9.2
Peripheral Muxing
9.10
Internal Pullup Configuration Requirements
9.11
Software
9.11.1
GPIO Registers to Driverlib Functions
9.11.2
GPIO Examples
9.11.2.1
Device GPIO Setup
9.11.2.2
Device GPIO Toggle
9.11.2.3
Device GPIO Interrupt
9.11.2.4
External Interrupt (XINT)
9.11.3
LED Examples
9.12
GPIO Registers
9.12.1
GPIO Base Address Table
9.12.2
GPIO_CTRL_REGS Registers
9.12.3
GPIO_DATA_REGS Registers
9.12.4
GPIO_DATA_READ_REGS Registers
10
Crossbar (X-BAR)
10.1
Input X-BAR and CLB Input X-BAR
10.1.1
CLB Input X-BAR
10.2
ePWM, CLB, and GPIO Output X-BAR
10.2.1
ePWM X-BAR
10.2.1.1
ePWM X-BAR Architecture
10.2.2
CLB X-BAR
10.2.2.1
CLB X-BAR Architecture
10.2.3
GPIO Output X-BAR
10.2.3.1
GPIO Output X-BAR Architecture
10.2.4
X-BAR Flags
10.3
Software
10.3.1
XBAR Registers to Driverlib Functions
10.3.2
INPUTXBAR Registers to Driverlib Functions
10.3.3
OUTPUTXBAR Registers to Driverlib Functions
10.4
XBAR Registers
10.4.1
XBAR Base Address Table
10.4.2
INPUT_XBAR_REGS Registers
10.4.3
XBAR_REGS Registers
10.4.4
EPWM_XBAR_REGS Registers
10.4.5
CLB_XBAR_REGS Registers
10.4.6
OUTPUT_XBAR_REGS Registers
10.4.7
OUTPUT_XBAR_REGS Registers
11
Direct Memory Access (DMA)
11.1
Introduction
11.1.1
Features
11.1.2
Block Diagram
11.2
Architecture
11.2.1
Peripheral Interrupt Event Trigger Sources
11.2.2
DMA Bus
11.3
Address Pointer and Transfer Control
11.4
Pipeline Timing and Throughput
11.5
CPU and CLA Arbitration
11.6
Channel Priority
11.6.1
Round-Robin Mode
11.6.2
Channel 1 High-Priority Mode
11.7
Overrun Detection Feature
11.8
Software
11.8.1
DMA Registers to Driverlib Functions
11.8.2
DMA Examples
11.8.2.1
DMA GSRAM Transfer (dma_ex1_gsram_transfer)
11.8.2.2
DMA GSRAM Transfer (dma_ex2_gsram_transfer)
11.9
DMA Registers
11.9.1
DMA Base Address Table
11.9.2
DMA_REGS Registers
11.9.3
DMA_CH_REGS Registers
12
Embedded Real-time Analysis and Diagnostic (ERAD)
12.1
Introduction
12.1.1
ERAD Related Collateral
12.2
Enhanced Bus Comparator Unit
12.2.1
Enhanced Bus Comparator Unit Operations
12.2.2
Event Masking and Exporting
12.3
System Event Counter Unit
12.3.1
System Event Counter Modes
12.3.1.1
Counting Active Levels Versus Edges
12.3.1.2
Max Mode
12.3.1.3
Cumulative Mode
12.3.1.4
Input Signal Selection
12.3.2
Reset on Event
12.3.3
Operation Conditions
12.4
ERAD Ownership, Initialization and Reset
12.5
ERAD Programming Sequence
12.5.1
Hardware Breakpoint and Hardware Watch Point Programming Sequence
12.5.2
Timer and Counter Programming Sequence
12.6
Cyclic Redundancy Check Unit
12.6.1
CRC Unit Qualifier
12.6.2
CRC Unit Programming Sequence
12.7
Program Counter Trace
12.7.1
Functional Block Diagram
12.7.2
Trace Qualification Modes
12.7.2.1
Trace Qualifier Input Signals
12.7.3
Trace Memory
12.7.4
Trace Input Signal Conditioning
12.7.5
PC Trace Software Operation
12.7.6
Trace Operation in Debug Mode
12.8
Software
12.8.1
ERAD Registers to Driverlib Functions
12.8.2
ERAD Examples
12.8.2.1
ERAD Profiling Interrupts
12.8.2.2
ERAD Profile Function
12.8.2.3
ERAD Profile Function
12.8.2.4
ERAD HWBP Monitor Program Counter
12.8.2.5
ERAD HWBP Monitor Program Counter
12.8.2.6
ERAD Profile Function
12.8.2.7
ERAD HWBP Stack Overflow Detection
12.8.2.8
ERAD HWBP Stack Overflow Detection
12.8.2.9
ERAD Stack Overflow
12.8.2.10
ERAD Profile Interrupts CLA
12.8.2.11
ERAD Profiling Interrupts
12.8.2.12
ERAD Profiling Interrupts
12.8.2.13
ERAD MEMORY ACCESS RESTRICT
12.8.2.14
ERAD INTERRUPT ORDER
12.8.2.15
ERAD AND CLB
12.8.2.16
ERAD PWM PROTECTION
12.9
ERAD Registers
12.9.1
ERAD Base Address Table
12.9.2
ERAD_GLOBAL_REGS Registers
12.9.3
ERAD_HWBP_REGS Registers
12.9.4
ERAD_COUNTER_REGS Registers
12.9.5
ERAD_CRC_GLOBAL_REGS Registers
12.9.6
ERAD_CRC_REGS Registers
12.9.7
PCTRACE_REGS Registers
12.9.8
PCTRACE_BUFFER_REGS Registers
13
Analog Subsystem
13.1
Introduction
13.1.1
Features
13.1.2
Block Diagram
13.2
Optimizing Power-Up Time
13.3
Digital Inputs on ADC Pins (AIOs)
13.4
Digital Inputs and Outputs on ADC Pins (AGPIOs)
13.5
Analog Pins and Internal Connections
13.6
Software
13.6.1
ASYSCTL Registers to Driverlib Functions
13.7
ASBSYS Registers
13.7.1
ASBSYS Base Address Table
13.7.2
ANALOG_SUBSYS_REGS Registers
14
Analog-to-Digital Converter (ADC)
14.1
Introduction
14.1.1
ADC Related Collateral
14.1.2
Features
14.1.3
Block Diagram
14.2
ADC Configurability
14.2.1
Clock Configuration
14.2.2
Resolution
14.2.3
Voltage Reference
14.2.3.1
External Reference Mode
14.2.3.2
Internal Reference Mode
14.2.3.3
Ganged References
14.2.3.4
Selecting Reference Mode
14.2.4
Signal Mode
14.2.5
Expected Conversion Results
14.2.6
Interpreting Conversion Results
14.3
SOC Principle of Operation
14.3.1
SOC Configuration
14.3.2
Trigger Operation
14.3.2.1
Global Software Trigger
14.3.2.2
Trigger Repeaters
14.3.2.2.1
Oversampling Mode
14.3.2.2.2
Undersampling Mode
14.3.2.2.3
Trigger Phase Delay
14.3.2.2.4
Re-trigger Spread
14.3.2.2.5
Trigger Repeater Configuration
14.3.2.2.5.1
Register Shadow Updates
14.3.2.2.6
Re-Trigger Logic
14.3.2.2.7
Multi-Path Triggering Behavior
14.3.3
ADC Acquisition (Sample and Hold) Window
14.3.4
Sample Capacitor Reset
14.3.5
ADC Input Models
14.3.6
Channel Selection
14.3.6.1
External Channel Selection
14.3.6.1.1
External Channel Selection Timing
14.4
SOC Configuration Examples
14.4.1
Single Conversion from ePWM Trigger
14.4.2
Multiple Conversions from CPU Timer Trigger
14.4.3
Software Triggering of SOCs
14.5
ADC Conversion Priority
14.6
Burst Mode
14.6.1
Burst Mode Example
14.6.2
Burst Mode Priority Example
14.7
EOC and Interrupt Operation
14.7.1
Interrupt Overflow
14.7.2
Continue to Interrupt Mode
14.7.3
Early Interrupt Configuration Mode
14.8
Post-Processing Blocks
14.8.1
PPB Offset Correction
14.8.2
PPB Error Calculation
14.8.3
PPB Result Delta Calculation
14.8.4
PPB Limit Detection and Zero-Crossing Detection
14.8.4.1
PPB Digital Trip Filter
14.8.5
PPB Sample Delay Capture
14.8.6
PPB Oversampling
14.8.6.1
Accumulation, Average, Minimum, and Maximum Functions
14.8.6.2
Outlier Rejection
14.9
Power-Up Sequence
14.10
ADC Calibration
14.10.1
ADC Zero Offset Calibration
14.11
ADC Timings
14.11.1
ADC Timing Diagrams
14.11.2
Post-Processing Block Timings
14.12
Additional Information
14.12.1
Ensuring Synchronous Operation
14.12.1.1
Basic Synchronous Operation
14.12.1.2
Synchronous Operation with Multiple Trigger Sources
14.12.1.3
Synchronous Operation with Uneven SOC Numbers
14.12.1.4
Non-overlapping Conversions
14.12.2
Choosing an Acquisition Window Duration
14.12.3
Achieving Simultaneous Sampling
14.12.4
Result Register Mapping
14.12.5
Internal Temperature Sensor
14.12.6
Designing an External Reference Circuit
14.12.7
ADC-DAC Loopback Testing
14.12.8
Internal Test Mode
14.12.9
ADC Gain and Offset Calibration
14.13
Software
14.13.1
ADC Registers to Driverlib Functions
14.13.2
ADC Examples
14.13.2.1
ADC Software Triggering
14.13.2.2
ADC ePWM Triggering
14.13.2.3
ADC Temperature Sensor Conversion
14.13.2.4
ADC Synchronous SOC Software Force (adc_soc_software_sync)
14.13.2.5
ADC Continuous Triggering (adc_soc_continuous)
14.13.2.6
ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
14.13.2.7
ADC PPB Offset (adc_ppb_offset)
14.13.2.8
ADC PPB Limits (adc_ppb_limits)
14.13.2.9
ADC PPB Delay Capture (adc_ppb_delay)
14.13.2.10
ADC ePWM Triggering Multiple SOC
14.13.2.11
ADC Burst Mode
14.13.2.12
ADC Burst Mode Oversampling
14.13.2.13
ADC SOC Oversampling
14.13.2.14
ADC PPB PWM trip (adc_ppb_pwm_trip)
14.14
ADC Registers
14.14.1
ADC Base Address Table
14.14.2
ADC_RESULT_REGS Registers
14.14.3
ADC_REGS Registers
15
Buffered Digital-to-Analog Converter (DAC)
15.1
Introduction
15.1.1
DAC Related Collateral
15.1.2
Features
15.1.3
Block Diagram
15.2
Using the DAC
15.2.1
Initialization Sequence
15.2.2
DAC Offset Adjustment
15.2.3
EPWMSYNCPER Signal
15.3
Lock Registers
15.4
Software
15.4.1
DAC Registers to Driverlib Functions
15.4.2
DAC Examples
15.4.2.1
Buffered DAC Enable
15.4.2.2
Buffered DAC Random
15.4.2.3
Buffered DAC Sine (buffdac_sine)
15.5
DAC Registers
15.5.1
DAC Base Address Table
15.5.2
DAC_REGS Registers
16
Comparator Subsystem (CMPSS)
16.1
Introduction
16.1.1
CMPSS Related Collateral
16.1.2
Features
16.1.3
Block Diagram
16.2
Comparator
16.3
Reference DAC
16.4
Ramp Generator
16.4.1
Ramp Generator Overview
16.4.2
Ramp Generator Behavior
16.4.3
Ramp Generator Behavior at Corner Cases
16.5
Digital Filter
16.5.1
Filter Initialization Sequence
16.6
Using the CMPSS
16.6.1
LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
16.6.2
Synchronizer, Digital Filter, and Latch Delays
16.6.3
Calibrating the CMPSS
16.6.4
Enabling and Disabling the CMPSS Clock
16.7
CMPSS DAC Output
16.8
Software
16.8.1
CMPSS Registers to Driverlib Functions
16.8.2
CMPSS Examples
16.8.2.1
CMPSS Asynchronous Trip
16.8.2.2
CMPSS Digital Filter Configuration
16.9
CMPSS Registers
16.9.1
CMPSS Base Address Table
16.9.2
CMPSS_REGS Registers
17
Programmable Gain Amplifier (PGA)
17.1
Programmable Gain Amplifier (PGA) Overview
17.1.1
Features
17.1.2
Block Diagram
17.2
Linear Output Range
17.3
Gain Values
17.4
Modes of Operation
17.4.1
Buffer Mode
17.4.2
Standalone Mode
17.4.3
Non-inverting Mode
17.4.4
Subtractor Mode
17.5
External Filtering
17.5.1
Low-Pass Filter Using Internal Filter Resistor and External Capacitor
17.5.2
Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
17.6
Error Calibration
17.6.1
Offset Error
17.6.2
Gain Error
17.7
Chopping Feature
17.8
Enabling and Disabling the PGA Clock
17.9
Lock Register
17.10
Analog Front-End Integration
17.10.1
Buffered DAC
17.10.2
Analog-to-Digital Converter (ADC)
17.10.2.1
Unfiltered Acquisition Window
17.10.2.2
Filtered Acquisition Window
17.10.3
Comparator Subsystem (CMPSS)
17.10.4
PGA_NEG_SHARED Feature
17.10.5
Alternate Functions
17.11
Examples
17.11.1
Non-Inverting Amplifier Using Non-Inverting Mode
17.11.2
Buffer Mode
17.11.3
Low-Side Current Sensing
17.11.4
Bidirectional Current Sensing
17.12
Software
17.12.1
PGA Registers to Driverlib Functions
17.12.2
PGA Examples
17.12.2.1
PGA DAC-ADC External Loopback Example
17.13
PGA Registers
17.13.1
PGA Base Address Table
17.13.2
PGA_REGS Registers
18
Enhanced Pulse Width Modulator (ePWM)
18.1
Introduction
18.1.1
EPWM Related Collateral
18.1.2
Submodule Overview
18.2
Configuring Device Pins
18.3
ePWM Modules Overview
18.4
Time-Base (TB) Submodule
18.4.1
Purpose of the Time-Base Submodule
18.4.2
Controlling and Monitoring the Time-Base Submodule
18.4.3
Calculating PWM Period and Frequency
18.4.3.1
Time-Base Period Shadow Register
18.4.3.2
Time-Base Clock Synchronization
18.4.3.3
Time-Base Counter Synchronization
18.4.3.4
ePWM SYNC Selection
18.4.4
Phase Locking the Time-Base Clocks of Multiple ePWM Modules
18.4.5
Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
18.4.6
Time-Base Counter Modes and Timing Waveforms
18.4.7
Global Load
18.4.7.1
Global Load Pulse Pre-Scalar
18.4.7.2
One-Shot Load Mode
18.4.7.3
One-Shot Sync Mode
18.5
Counter-Compare (CC) Submodule
18.5.1
Purpose of the Counter-Compare Submodule
18.5.2
Controlling and Monitoring the Counter-Compare Submodule
18.5.3
Operational Highlights for the Counter-Compare Submodule
18.5.4
Count Mode Timing Waveforms
18.6
Action-Qualifier (AQ) Submodule
18.6.1
Purpose of the Action-Qualifier Submodule
18.6.2
Action-Qualifier Submodule Control and Status Register Definitions
18.6.3
Action-Qualifier Event Priority
18.6.4
AQCTLA and AQCTLB Shadow Mode Operations
18.6.5
Configuration Requirements for Common Waveforms
18.7
Dead-Band Generator (DB) Submodule
18.7.1
Purpose of the Dead-Band Submodule
18.7.2
Dead-band Submodule Additional Operating Modes
18.7.3
Operational Highlights for the Dead-Band Submodule
18.8
PWM Chopper (PC) Submodule
18.8.1
Purpose of the PWM Chopper Submodule
18.8.2
Operational Highlights for the PWM Chopper Submodule
18.8.3
Waveforms
18.8.3.1
One-Shot Pulse
18.8.3.2
Duty Cycle Control
18.9
Trip-Zone (TZ) Submodule
18.9.1
Purpose of the Trip-Zone Submodule
18.9.2
Operational Highlights for the Trip-Zone Submodule
18.9.2.1
Trip-Zone Configurations
18.9.3
Generating Trip Event Interrupts
18.10
Event-Trigger (ET) Submodule
18.10.1
Operational Overview of the ePWM Event-Trigger Submodule
18.11
Digital Compare (DC) Submodule
18.11.1
Purpose of the Digital Compare Submodule
18.11.2
Enhanced Trip Action Using CMPSS
18.11.3
Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
18.11.4
Operation Highlights of the Digital Compare Submodule
18.11.4.1
Digital Compare Events
18.11.4.2
Event Filtering
18.11.4.3
Valley Switching
18.12
ePWM Crossbar (X-BAR)
18.13
Applications to Power Topologies
18.13.1
Overview of Multiple Modules
18.13.2
Key Configuration Capabilities
18.13.3
Controlling Multiple Buck Converters With Independent Frequencies
18.13.4
Controlling Multiple Buck Converters With Same Frequencies
18.13.5
Controlling Multiple Half H-Bridge (HHB) Converters
18.13.6
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
18.13.7
Practical Applications Using Phase Control Between PWM Modules
18.13.8
Controlling a 3-Phase Interleaved DC/DC Converter
18.13.9
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
18.13.10
Controlling a Peak Current Mode Controlled Buck Module
18.13.11
Controlling H-Bridge LLC Resonant Converter
18.14
Register Lock Protection
18.15
High-Resolution Pulse Width Modulator (HRPWM)
18.15.1
Operational Description of HRPWM
18.15.1.1
Controlling the HRPWM Capabilities
18.15.1.2
HRPWM Source Clock
18.15.1.3
Configuring the HRPWM
18.15.1.4
Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
18.15.1.5
Principle of Operation
18.15.1.5.1
Edge Positioning
18.15.1.5.2
Scaling Considerations
18.15.1.5.3
Duty Cycle Range Limitation
18.15.1.5.4
High-Resolution Period
18.15.1.5.4.1
High-Resolution Period Configuration
18.15.1.6
Deadband High-Resolution Operation
18.15.1.7
Scale Factor Optimizing Software (SFO)
18.15.1.8
HRPWM Examples Using Optimized Assembly Code
18.15.1.8.1
#Defines for HRPWM Header Files
18.15.1.8.2
Implementing a Simple Buck Converter
18.15.1.8.2.1
HRPWM Buck Converter Initialization Code
18.15.1.8.2.2
HRPWM Buck Converter Run-Time Code
18.15.1.8.3
Implementing a DAC Function Using an R+C Reconstruction Filter
18.15.1.8.3.1
PWM DAC Function Initialization Code
18.15.1.8.3.2
PWM DAC Function Run-Time Code
18.15.2
SFO Library Software - SFO_TI_Build_V8.lib
18.15.2.1
Scale Factor Optimizer Function - int SFO()
18.15.2.2
Software Usage
18.15.2.2.1
A Sample of How to Add "Include" Files
912
18.15.2.2.2
Declaring an Element
914
18.15.2.2.3
Initializing With a Scale Factor Value
916
18.15.2.2.4
SFO Function Calls
18.16
Software
18.16.1
EPWM Registers to Driverlib Functions
18.16.2
EPWMXBAR Registers to Driverlib Functions
18.16.3
HRPWM Registers to Driverlib Functions
18.16.4
EPWM Examples
18.16.4.1
ePWM Trip Zone
18.16.4.2
ePWM Up Down Count Action Qualifier
18.16.4.3
ePWM Synchronization
18.16.4.4
ePWM Digital Compare
18.16.4.5
ePWM Digital Compare Event Filter Blanking Window
18.16.4.6
ePWM Valley Switching
18.16.4.7
ePWM Digital Compare Edge Filter
18.16.4.8
ePWM Deadband
18.16.4.9
ePWM DMA
18.16.4.10
ePWM Chopper
18.16.4.11
EPWM Configure Signal
18.16.4.12
Realization of Monoshot mode
18.16.4.13
EPWM Action Qualifier (epwm_up_aq)
18.16.5
HRPWM Examples
18.16.5.1
HRPWM Duty Control with SFO
18.16.5.2
HRPWM Slider
18.16.5.3
HRPWM Period Control
18.16.5.4
HRPWM Duty Control with UPDOWN Mode
18.16.5.5
HRPWM Slider Test
18.16.5.6
HRPWM Duty Up Count
18.16.5.7
HRPWM Period Up-Down Count
18.17
EPWM Registers
18.17.1
EPWM Base Address Table
18.17.2
EPWM_REGS Registers
19
Enhanced Capture (eCAP)
19.1
Introduction
19.1.1
Features
19.1.2
ECAP Related Collateral
19.2
Description
19.3
Configuring Device Pins for the eCAP
19.4
Capture and APWM Operating Mode
19.5
Capture Mode Description
19.5.1
Event Prescaler
19.5.2
Edge Polarity Select and Qualifier
19.5.3
Continuous/One-Shot Control
19.5.4
32-Bit Counter and Phase Control
19.5.5
CAP1-CAP4 Registers
19.5.6
eCAP Synchronization
19.5.6.1
Example 1 - Using SWSYNC with ECAP Module
19.5.7
Interrupt Control
19.5.8
DMA Interrupt
19.5.9
Shadow Load and Lockout Control
19.5.10
APWM Mode Operation
19.6
Application of the eCAP Module
19.6.1
Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
19.6.2
Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
19.6.3
Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
19.6.4
Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
19.7
Application of the APWM Mode
19.7.1
Example 1 - Simple PWM Generation (Independent Channels)
19.8
Software
19.8.1
ECAP Registers to Driverlib Functions
19.8.2
ECAP Examples
19.8.2.1
eCAP APWM Example
19.8.2.2
eCAP Capture PWM Example
19.8.2.3
eCAP APWM Phase-shift Example
19.9
ECAP Registers
19.9.1
ECAP Base Address Table
19.9.2
ECAP_REGS Registers
20
Enhanced Quadrature Encoder Pulse (eQEP)
20.1
Introduction
20.1.1
EQEP Related Collateral
20.2
Configuring Device Pins
20.3
Description
20.3.1
EQEP Inputs
20.3.2
Functional Description
20.3.3
eQEP Memory Map
20.4
Quadrature Decoder Unit (QDU)
20.4.1
Position Counter Input Modes
20.4.1.1
Quadrature Count Mode
20.4.1.2
Direction-Count Mode
20.4.1.3
Up-Count Mode
20.4.1.4
Down-Count Mode
20.4.2
eQEP Input Polarity Selection
20.4.3
Position-Compare Sync Output
20.5
Position Counter and Control Unit (PCCU)
20.5.1
Position Counter Operating Modes
20.5.1.1
Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
20.5.1.2
Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
20.5.1.3
Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
20.5.1.4
Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
20.5.2
Position Counter Latch
20.5.2.1
Index Event Latch
20.5.2.2
Strobe Event Latch
20.5.3
Position Counter Initialization
20.5.4
eQEP Position-compare Unit
20.6
eQEP Edge Capture Unit
20.7
eQEP Watchdog
20.8
eQEP Unit Timer Base
20.9
QMA Module
20.9.1
Modes of Operation
20.9.1.1
QMA Mode-1 (QMACTRL[MODE]=1)
20.9.1.2
QMA Mode-2 (QMACTRL[MODE]=2)
20.9.2
Interrupt and Error Generation
20.10
eQEP Interrupt Structure
20.11
Software
20.11.1
EQEP Registers to Driverlib Functions
20.11.2
EQEP Examples
20.11.2.1
Frequency Measurement Using eQEP
20.11.2.2
Position and Speed Measurement Using eQEP
20.11.2.3
Frequency Measurement Using eQEP via unit timeout interrupt
20.11.2.4
Motor speed and direction measurement using eQEP via unit timeout interrupt
20.12
EQEP Registers
20.12.1
EQEP Base Address Table
20.12.2
EQEP_REGS Registers
21
Serial Peripheral Interface (SPI)
21.1
Introduction
21.1.1
Features
21.1.2
SPI Related Collateral
21.1.3
Block Diagram
21.2
System-Level Integration
21.2.1
SPI Module Signals
21.2.2
Configuring Device Pins
21.2.2.1
GPIOs Required for High-Speed Mode
21.2.3
SPI Interrupts
21.2.4
DMA Support
21.3
SPI Operation
21.3.1
Introduction to Operation
21.3.2
Controller Mode
21.3.3
Peripheral Mode
21.3.4
Data Format
21.3.4.1
Transmission of Bit from SPIRXBUF
21.3.5
Baud Rate Selection
21.3.5.1
Baud Rate Determination
21.3.5.2
Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
21.3.6
SPI Clocking Schemes
21.3.7
SPI FIFO Description
21.3.8
SPI DMA Transfers
21.3.8.1
Transmitting Data Using SPI with DMA
21.3.8.2
Receiving Data Using SPI with DMA
21.3.9
SPI High-Speed Mode
21.3.10
SPI 3-Wire Mode Description
21.4
Programming Procedure
21.4.1
Initialization Upon Reset
21.4.2
Configuring the SPI
21.4.3
Configuring the SPI for High-Speed Mode
21.4.4
Data Transfer Example
21.4.5
SPI 3-Wire Mode Code Examples
21.4.5.1
3-Wire Controller Mode Transmit
1062
21.4.5.2.1
3-Wire Controller Mode Receive
1064
21.4.5.2.1
3-Wire Peripheral Mode Transmit
1066
21.4.5.2.1
3-Wire Peripheral Mode Receive
21.4.6
SPI STEINV Bit in Digital Audio Transfers
21.5
Software
21.5.1
SPI Registers to Driverlib Functions
21.5.2
SPI Examples
21.5.2.1
SPI Digital Loopback
21.5.2.2
SPI Digital Loopback with FIFO Interrupts
21.5.2.3
SPI Digital External Loopback without FIFO Interrupts
21.5.2.4
SPI Digital External Loopback with FIFO Interrupts
21.5.2.5
SPI Digital Loopback with DMA
21.5.2.6
SPI EEPROM
21.5.2.7
SPI DMA EEPROM
21.6
SPI Registers
21.6.1
SPI Base Address Table
21.6.2
SPI_REGS Registers
22
Serial Communications Interface (SCI)
22.1
Introduction
22.1.1
Features
22.1.2
SCI Related Collateral
22.1.3
Block Diagram
22.2
Architecture
22.3
SCI Module Signal Summary
22.4
Configuring Device Pins
22.5
Multiprocessor and Asynchronous Communication Modes
22.6
SCI Programmable Data Format
22.7
SCI Multiprocessor Communication
22.7.1
Recognizing the Address Byte
22.7.2
Controlling the SCI TX and RX Features
22.7.3
Receipt Sequence
22.8
Idle-Line Multiprocessor Mode
22.8.1
Idle-Line Mode Steps
22.8.2
Block Start Signal
22.8.3
Wake-Up Temporary (WUT) Flag
22.8.3.1
Sending a Block Start Signal
22.8.4
Receiver Operation
22.9
Address-Bit Multiprocessor Mode
22.9.1
Sending an Address
22.10
SCI Communication Format
22.10.1
Receiver Signals in Communication Modes
22.10.2
Transmitter Signals in Communication Modes
22.11
SCI Port Interrupts
22.11.1
Break Detect
22.12
SCI Baud Rate Calculations
22.13
SCI Enhanced Features
22.13.1
SCI FIFO Description
22.13.2
SCI Auto-Baud
22.13.3
Autobaud-Detect Sequence
22.14
Software
22.14.1
SCI Registers to Driverlib Functions
22.14.2
SCI Examples
22.14.2.1
Tune Baud Rate via UART Example
22.14.2.2
SCI FIFO Digital Loop Back
22.14.2.3
SCI Digital Loop Back with Interrupts
22.14.2.4
SCI Echoback
22.14.2.5
stdout redirect example
22.15
SCI Registers
22.15.1
SCI Base Address Table
22.15.2
SCI_REGS Registers
23
Universal Serial Bus (USB) Controller
23.1
Introduction
23.1.1
Features
23.1.2
USB Related Collateral
23.1.3
Block Diagram
23.1.3.1
Signal Description
23.1.3.2
VBus Recommendations
23.2
Functional Description
23.2.1
Operation as a Device
23.2.1.1
Control and Configurable Endpoints
23.2.1.1.1
IN Transactions as a Device
23.2.1.1.2
Out Transactions as a Device
23.2.1.1.3
Scheduling
23.2.1.1.4
Additional Actions
23.2.1.1.5
Device Mode Suspend
23.2.1.1.6
Start of Frame
23.2.1.1.7
USB Reset
23.2.1.1.8
Connect/Disconnect
23.2.2
Operation as a Host
23.2.2.1
Endpoint Registers
23.2.2.2
IN Transactions as a Host
23.2.2.3
OUT Transactions as a Host
23.2.2.4
Transaction Scheduling
23.2.2.5
USB Hubs
23.2.2.6
Babble
23.2.2.7
Host SUSPEND
23.2.2.8
USB RESET
23.2.2.9
Connect/Disconnect
23.2.3
DMA Operation
23.2.4
Address/Data Bus Bridge
23.3
Initialization and Configuration
23.3.1
Pin Configuration
23.3.2
Endpoint Configuration
23.4
USB Global Interrupts
23.5
Software
23.5.1
USB Examples
23.5.1.1
USB CDC serial example
23.5.1.2
USB HID Mouse Device
23.5.1.3
USB Device Keyboard
23.5.1.4
USB Generic Bulk Device
23.5.1.5
USB HID Mouse Host
23.5.1.6
USB HID Keyboard Host
23.5.1.7
USB Mass Storage Class Host
23.5.1.8
USB Dual Detect
23.5.1.9
USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk)
23.5.1.10
USB HUB Host example
23.6
USB Registers
23.6.1
USB Base Address Table
23.6.2
USB_REGS Registers
24
Fast Serial Interface (FSI)
24.1
Introduction
24.1.1
FSI Related Collateral
24.1.2
FSI Features
24.2
System-level Integration
24.2.1
CPU Interface
24.2.2
Signal Description
24.2.2.1
Configuring Device Pins
24.2.3
FSI Interrupts
24.2.3.1
Transmitter Interrupts
24.2.3.2
Receiver Interrupts
24.2.3.3
Configuring Interrupts
24.2.3.4
Handling Interrupts
24.2.4
CLA Task Triggering
24.2.5
DMA Interface
24.2.6
External Frame Trigger Mux
24.3
FSI Functional Description
24.3.1
Introduction to Operation
24.3.2
FSI Transmitter Module
24.3.2.1
Initialization
24.3.2.2
FSI_TX Clocking
24.3.2.3
Transmitting Frames
24.3.2.3.1
Software Triggered Frames
24.3.2.3.2
Externally Triggered Frames
24.3.2.3.3
Ping Frame Generation
24.3.2.3.3.1
Automatic Ping Frames
24.3.2.3.3.2
Software Triggered Ping Frame
24.3.2.3.3.3
Externally Triggered Ping Frame
24.3.2.3.4
Transmitting Frames with DMA
24.3.2.4
Transmit Buffer Management
24.3.2.5
CRC Submodule
24.3.2.6
Conditions in Which the Transmitter Must Undergo a Soft Reset
24.3.2.7
Reset
24.3.3
FSI Receiver Module
24.3.3.1
Initialization
24.3.3.2
FSI_RX Clocking
24.3.3.3
Receiving Frames
24.3.3.3.1
Receiving Frames with DMA
24.3.3.4
Ping Frame Watchdog
24.3.3.5
Frame Watchdog
24.3.3.6
Delay Line Control
24.3.3.7
Buffer Management
24.3.3.8
CRC Submodule
24.3.3.9
Using the Zero Bits of the Receiver Tag Registers
24.3.3.10
Conditions in Which the Receiver Must Undergo a Soft Reset
24.3.3.11
FSI_RX Reset
24.3.4
Frame Format
24.3.4.1
FSI Frame Phases
24.3.4.2
Frame Types
24.3.4.2.1
Ping Frames
24.3.4.2.2
Error Frames
24.3.4.2.3
Data Frames
24.3.4.3
Multi-Lane Transmission
24.3.5
Flush Sequence
24.3.6
Internal Loopback
24.3.7
CRC Generation
24.3.8
ECC Module
24.3.9
Tag Matching
24.3.10
User Data Filtering (UDATA Matching)
24.3.11
TDM Configurations
24.3.12
FSI Trigger Generation
24.3.13
FSI-SPI Compatibility Mode
24.3.13.1
Available SPI Modes
24.3.13.1.1
FSITX as SPI Controller, Transmit Only
24.3.13.1.1.1
Initialization
24.3.13.1.1.2
Operation
24.3.13.1.2
FSIRX as SPI Peripheral, Receive Only
24.3.13.1.2.1
Initialization
24.3.13.1.2.2
Operation
24.3.13.1.3
FSITX and FSIRX Emulating a Full Duplex SPI Controller
24.3.13.1.3.1
Initialization
24.3.13.1.3.2
Operation
24.4
FSI Programing Guide
24.4.1
Establishing the Communication Link
24.4.1.1
Establishing the Communication Link from the Main Device
24.4.1.2
Establishing the Communication Link from the Remote Device
24.4.2
Register Protection
24.4.3
Emulation Mode
24.5
Software
24.5.1
FSI Registers to Driverlib Functions
24.5.2
FSI Examples
24.5.2.1
FSI Loopback:CPU Control
24.5.2.2
FSI DMA frame transfers:DMA Control
24.5.2.3
FSI data transfer by external trigger
24.5.2.4
FSI data transfers upon CPU Timer event
24.5.2.5
FSI and SPI communication(fsi_ex6_spi_main_tx)
24.5.2.6
FSI and SPI communication(fsi_ex7_spi_remote_rx)
24.5.2.7
FSI P2Point Connection:Rx Side
24.5.2.8
FSI P2Point Connection:Tx Side
24.6
FSI Registers
24.6.1
FSI Base Address Table
24.6.2
FSI_TX_REGS Registers
24.6.3
FSI_RX_REGS Registers
25
Inter-Integrated Circuit Module (I2C)
25.1
Introduction
25.1.1
I2C Related Collateral
25.1.2
Features
25.1.3
Features Not Supported
25.1.4
Functional Overview
25.1.5
Clock Generation
25.1.6
I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
25.1.6.1
Formula for the Controller Clock Period
25.2
Configuring Device Pins
25.3
I2C Module Operational Details
25.3.1
Input and Output Voltage Levels
25.3.2
Selecting Pullup Resistors
25.3.3
Data Validity
25.3.4
Operating Modes
25.3.5
I2C Module START and STOP Conditions
25.3.6
Non-repeat Mode versus Repeat Mode
25.3.7
Serial Data Formats
25.3.7.1
7-Bit Addressing Format
25.3.7.2
10-Bit Addressing Format
25.3.7.3
Free Data Format
25.3.7.4
Using a Repeated START Condition
25.3.8
Clock Synchronization
25.3.9
Clock Stretching
25.3.10
Arbitration
25.3.11
Digital Loopback Mode
25.3.12
NACK Bit Generation
25.4
Interrupt Requests Generated by the I2C Module
25.4.1
Basic I2C Interrupt Requests
25.4.2
I2C FIFO Interrupts
25.5
Resetting or Disabling the I2C Module
25.6
Software
25.6.1
I2C Registers to Driverlib Functions
25.6.2
I2C Examples
25.6.2.1
C28x-I2C Library source file for FIFO interrupts
25.6.2.2
C28x-I2C Library source file for FIFO using polling
25.6.2.3
C28x-I2C Library source file for FIFO interrupts
25.6.2.4
I2C Digital Loopback with FIFO Interrupts
25.6.2.5
I2C EEPROM
25.6.2.6
I2C Digital External Loopback with FIFO Interrupts
25.6.2.7
I2C EEPROM
25.6.2.8
I2C controller target communication using FIFO interrupts
25.6.2.9
I2C EEPROM
25.6.2.10
I2C Extended Clock Stretching Target RX
25.6.2.11
I2C Extended Clock Stretching Controller TX
25.7
I2C Registers
25.7.1
I2C Base Address Table
25.7.2
I2C_REGS Registers
26
Power Management Bus Module (PMBus)
26.1
Introduction
26.1.1
PMBUS Related Collateral
26.1.2
Features
26.1.3
Block Diagram
26.2
Configuring Device Pins
26.3
Target Mode Operation
26.3.1
Configuration
26.3.2
Message Handling
26.3.2.1
Quick Command
26.3.2.2
Send Byte
26.3.2.3
Receive Byte
26.3.2.4
Write Byte and Write Word
26.3.2.5
Read Byte and Read Word
26.3.2.6
Process Call
26.3.2.7
Block Write
26.3.2.8
Block Read
26.3.2.9
Block Write-Block Read Process Call
26.3.2.10
Alert Response
26.3.2.11
Extended Command
26.3.2.12
Group Command
26.4
Controller Mode Operation
26.4.1
Configuration
26.4.2
Message Handling
26.4.2.1
Quick Command
26.4.2.2
Send Byte
26.4.2.3
Receive Byte
26.4.2.4
Write Byte and Write Word
26.4.2.5
Read Byte and Read Word
26.4.2.6
Process Call
26.4.2.7
Block Write
26.4.2.8
Block Read
26.4.2.9
Block Write-Block Read Process Call
26.4.2.10
Alert Response
26.4.2.11
Extended Command
26.4.2.12
Group Command
26.5
Software
26.5.1
PMBUS Registers to Driverlib Functions
26.6
PMBUS Registers
26.6.1
PMBUS Base Address Table
26.6.2
PMBUS_REGS Registers
27
Modular Controller Area Network (MCAN)
27.1
MCAN Introduction
27.1.1
MCAN Related Collateral
27.1.2
MCAN Features
27.2
MCAN Environment
27.3
CAN Network Basics
27.4
MCAN Integration
27.5
MCAN Functional Description
27.5.1
Module Clocking Requirements
27.5.2
Interrupt Requests
27.5.3
Operating Modes
27.5.3.1
Software Initialization
27.5.3.2
Normal Operation
27.5.3.3
CAN FD Operation
27.5.4
Transmitter Delay Compensation
27.5.4.1
Description
27.5.4.2
Transmitter Delay Compensation Measurement
27.5.5
Restricted Operation Mode
27.5.6
Bus Monitoring Mode
27.5.7
Disabled Automatic Retransmission (DAR) Mode
27.5.7.1
Frame Transmission in DAR Mode
27.5.8
Clock Stop Mode
27.5.8.1
Suspend Mode
27.5.8.2
Wakeup Request
27.5.9
Test Modes
27.5.9.1
External Loop Back Mode
27.5.9.2
Internal Loop Back Mode
27.5.10
Timestamp Generation
27.5.10.1
External Timestamp Counter
27.5.11
Timeout Counter
27.5.12
Safety
27.5.12.1
ECC Wrapper
27.5.12.2
ECC Aggregator
27.5.12.2.1
ECC Aggregator Overview
27.5.12.2.2
ECC Aggregator Registers
27.5.12.3
Reads to ECC Control and Status Registers
27.5.12.4
ECC Interrupts
27.5.13
Rx Handling
27.5.13.1
Acceptance Filtering
27.5.13.1.1
Range Filter
27.5.13.1.2
Filter for Specific IDs
27.5.13.1.3
Classic Bit Mask Filter
27.5.13.1.4
Standard Message ID Filtering
27.5.13.1.5
Extended Message ID Filtering
27.5.13.2
Rx FIFOs
27.5.13.2.1
Rx FIFO Blocking Mode
27.5.13.2.2
Rx FIFO Overwrite Mode
27.5.13.3
Dedicated Rx Buffers
27.5.13.3.1
Rx Buffer Handling
27.5.14
Tx Handling
27.5.14.1
Transmit Pause
27.5.14.2
Dedicated Tx Buffers
27.5.14.3
Tx FIFO
27.5.14.4
Tx Queue
27.5.14.5
Mixed Dedicated Tx Buffers/Tx FIFO
27.5.14.6
Mixed Dedicated Tx Buffers/Tx Queue
27.5.14.7
Transmit Cancellation
27.5.14.8
Tx Event Handling
27.5.15
FIFO Acknowledge Handling
27.5.16
Message RAM
27.5.16.1
Message RAM Configuration
27.5.16.2
Rx Buffer and FIFO Element
27.5.16.3
Tx Buffer Element
27.5.16.4
Tx Event FIFO Element
27.5.16.5
Standard Message ID Filter Element
27.5.16.6
Extended Message ID Filter Element
27.6
Software
27.6.1
MCAN Registers to Driverlib Functions
27.6.2
MCAN Examples
27.6.2.1
MCAN Internal Loopback with Interrupt
27.6.2.2
MCAN Loopback with Interrupts Example Using SYSCONFIG Tool
27.6.2.3
MCAN receive using Rx Buffer
27.6.2.4
MCAN External Reception (with mask filter) into RX-FIFO1
27.6.2.5
MCAN Classic frames transmission using Tx Buffer
27.6.2.6
MCAN External Reception (with RANGE filter) into RX-FIFO1
27.6.2.7
MCAN External Transmit using Tx Buffer
27.6.2.8
MCAN receive using Rx Buffer
27.6.2.9
MCAN Internal Loopback with Interrupt
27.6.2.10
MCAN External Transmit using Tx Buffer
27.7
MCAN Registers
27.7.1
MCAN Base Address Table
27.7.2
MCANSS_REGS Registers
27.7.3
MCAN_REGS Registers
27.7.4
MCAN_ERROR_REGS Registers
28
Local Interconnect Network (LIN)
28.1
Introduction
28.1.1
SCI Features
28.1.2
LIN Features
28.1.3
LIN Related Collateral
28.1.4
Block Diagram
28.2
Serial Communications Interface Module
28.2.1
SCI Communication Formats
28.2.1.1
SCI Frame Formats
28.2.1.2
SCI Asynchronous Timing Mode
28.2.1.3
SCI Baud Rate
28.2.1.3.1
Superfractional Divider, SCI Asynchronous Mode
28.2.1.4
SCI Multiprocessor Communication Modes
28.2.1.4.1
Idle-Line Multiprocessor Modes
28.2.1.4.2
Address-Bit Multiprocessor Mode
28.2.1.5
SCI Multibuffered Mode
28.2.2
SCI Interrupts
28.2.2.1
Transmit Interrupt
28.2.2.2
Receive Interrupt
28.2.2.3
WakeUp Interrupt
28.2.2.4
Error Interrupts
28.2.3
SCI DMA Interface
28.2.3.1
Receive DMA Requests
28.2.3.2
Transmit DMA Requests
28.2.4
SCI Configurations
28.2.4.1
Receiving Data
28.2.4.1.1
Receiving Data in Single-Buffer Mode
28.2.4.1.2
Receiving Data in Multibuffer Mode
28.2.4.2
Transmitting Data
28.2.4.2.1
Transmitting Data in Single-Buffer Mode
28.2.4.2.2
Transmitting Data in Multibuffer Mode
28.2.5
SCI Low-Power Mode
28.2.5.1
Sleep Mode for Multiprocessor Communication
28.3
Local Interconnect Network Module
28.3.1
LIN Communication Formats
28.3.1.1
LIN Standards
28.3.1.2
Message Frame
28.3.1.2.1
Message Header
28.3.1.2.2
Response
28.3.1.3
Synchronizer
28.3.1.4
Baud Rate
28.3.1.4.1
Fractional Divider
28.3.1.4.2
Superfractional Divider
28.3.1.4.2.1
Superfractional Divider In LIN Mode
28.3.1.5
Header Generation
28.3.1.5.1
Event Triggered Frame Handling
28.3.1.5.2
Header Reception and Adaptive Baud Rate
28.3.1.6
Extended Frames Handling
28.3.1.7
Timeout Control
28.3.1.7.1
No-Response Error (NRE)
28.3.1.7.2
Bus Idle Detection
28.3.1.7.3
Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
28.3.1.8
TXRX Error Detector (TED)
28.3.1.8.1
Bit Errors
28.3.1.8.2
Physical Bus Errors
28.3.1.8.3
ID Parity Errors
28.3.1.8.4
Checksum Errors
28.3.1.9
Message Filtering and Validation
28.3.1.10
Receive Buffers
28.3.1.11
Transmit Buffers
28.3.2
LIN Interrupts
28.3.3
Servicing LIN Interrupts
28.3.4
LIN DMA Interface
28.3.4.1
LIN Receive DMA Requests
28.3.4.2
LIN Transmit DMA Requests
28.3.5
LIN Configurations
28.3.5.1
Receiving Data
28.3.5.1.1
Receiving Data in Single-Buffer Mode
28.3.5.1.2
Receiving Data in Multibuffer Mode
28.3.5.2
Transmitting Data
28.3.5.2.1
Transmitting Data in Single-Buffer Mode
28.3.5.2.2
Transmitting Data in Multibuffer Mode
28.4
Low-Power Mode
28.4.1
Entering Sleep Mode
28.4.2
Wakeup
28.4.3
Wakeup Timeouts
28.5
Emulation Mode
28.6
Software
28.6.1
LIN Registers to Driverlib Functions
28.6.2
LIN Examples
28.6.2.1
LIN Internal Loopback with Interrupts
28.6.2.2
LIN SCI Mode Internal Loopback with Interrupts
28.6.2.3
LIN SCI MODE Internal Loopback with DMA
28.6.2.4
LIN Internal Loopback without interrupts(polled mode)
28.6.2.5
LIN SCI MODE (Single Buffer) Internal Loopback with DMA
28.7
LIN Registers
28.7.1
LIN Base Address Table
28.7.2
LIN_REGS Registers
29
Configurable Logic Block (CLB)
29.1
Introduction
29.1.1
CLB Related Collateral
29.2
Description
29.2.1
CLB Clock
29.3
CLB Input/Output Connection
29.3.1
Overview
29.3.2
CLB Input Selection
29.3.3
CLB Output Selection
29.3.4
CLB Output Signal Multiplexer
29.4
CLB Tile
29.4.1
Static Switch Block
29.4.2
Counter Block
29.4.2.1
Counter Description
29.4.2.2
Counter Operation
29.4.2.3
Serializer Mode
29.4.2.4
Linear Feedback Shift Register (LFSR) Mode
29.4.3
FSM Block
29.4.4
LUT4 Block
29.4.5
Output LUT Block
29.4.6
Asynchronous Output Conditioning (AOC) Block
29.4.7
High Level Controller (HLC)
29.4.7.1
High Level Controller Events
29.4.7.2
High Level Controller Instructions
29.4.7.3
<Src> and <Dest>
29.4.7.4
Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
29.5
CPU Interface
29.5.1
Register Description
29.5.2
Non-Memory Mapped Registers
29.6
DMA Access
29.7
CLB Data Export Through SPI RX Buffer
29.8
Software
29.8.1
CLB Registers to Driverlib Functions
29.8.2
CLBOUTPUTXBAR Registers to Driverlib Functions
29.8.3
CLBXBAR Registers to Driverlib Functions
29.8.4
CLB Examples
29.8.4.1
CLB Empty Project
29.8.4.2
CLB Combinational Logic
29.8.4.3
CLB GPIO Input Filter
29.8.4.4
CLB Auxilary PWM
29.8.4.5
CLB PWM Protection
29.8.4.6
CLB Event Window
29.8.4.7
CLB Signal Generator
29.8.4.8
CLB State Machine
29.8.4.9
CLB External Signal AND Gate
29.8.4.10
CLB Timer
29.8.4.11
CLB Timer Two States
29.8.4.12
CLB Interrupt Tag
29.8.4.13
CLB Output Intersect
29.8.4.14
CLB PUSH PULL
29.8.4.15
CLB Multi Tile
29.8.4.16
CLB Tile to Tile Delay
29.8.4.17
CLB Glue Logic
29.8.4.18
CLB based One-shot PWM
29.8.4.19
CLB AOC Control
29.8.4.20
CLB AOC Release Control
29.8.4.21
CLB XBARs
29.8.4.22
CLB AOC Control
29.8.4.23
CLB Serializer
29.8.4.24
CLB LFSR
29.8.4.25
CLB Lock Output Mask
29.8.4.26
CLB INPUT Pipeline Mode
29.8.4.27
CLB Clocking and PIPELINE Mode
29.8.4.28
CLB SPI Data Export
29.8.4.29
CLB SPI Data Export DMA
29.8.4.30
CLB Trip Zone Timestamp
29.8.4.31
CLB CRC
29.8.4.32
CLB TDM Serial Port
29.8.4.33
CLB LED Driver
29.9
CLB Registers
29.9.1
CLB Base Address Table
29.9.2
CLB_LOGIC_CONFIG_REGS Registers
29.9.3
CLB_LOGIC_CONTROL_REGS Registers
29.9.4
CLB_DATA_EXCHANGE_REGS Registers
30
Advanced Encryption Standard (AES) Accelerator
30.1
Introduction
30.1.1
AES Block Diagram
30.1.1.1
Interfaces
30.1.1.2
AES Subsystem
30.1.1.3
AES Wide-Bus Engine
30.1.2
AES Algorithm
30.2
AES Operating Modes
30.2.1
GCM Operation
30.2.2
CCM Operation
30.2.3
XTS Operation
30.2.4
ECB Feedback Mode
30.2.5
CBC Feedback Mode
30.2.6
CTR and ICM Feedback Modes
30.2.7
CFB Mode
30.2.8
F8 Mode
30.2.9
F9 Operation
30.2.10
CBC-MAC Operation
30.3
Extended and Combined Modes of Operations
30.3.1
GCM Protocol Operation
30.3.2
CCM Protocol Operation
30.3.3
Hardware Requests
30.4
AES Module Programming Guide
30.4.1
AES Low-Level Programming Models
30.4.1.1
Global Initialization
30.4.1.2
AES Operating Modes Configuration
30.4.1.3
AES Mode Configurations
30.4.1.4
AES Events Servicing
30.5
Software
30.5.1
AES Registers to Driverlib Functions
30.5.2
AES_SS Registers to Driverlib Functions
30.5.3
AES Examples
30.5.3.1
AES ECB Encryption Example
30.5.3.2
AES ECB De-cryption Example
30.5.3.3
AES GCM Encryption Example
30.5.3.4
AES GCM Decryption Example
30.6
AES Registers
30.6.1
AES Base Address Table
30.6.2
AES_REGS Registers
30.6.3
AES_SS_REGS Registers
31
Embedded Pattern Generator (EPG)
31.1
Introduction
31.1.1
Features
31.1.2
EPG Block Diagram
31.1.3
EPG Related Collateral
31.2
Clock Generator Modules
31.2.1
DCLK (50% duty cycle clock)
31.2.2
Clock Stop
31.3
Signal Generator Module
31.4
EPG Peripheral Signal Mux Selection
31.5
Application Software Notes
31.6
EPG Example Use Cases
31.6.1
EPG Example: Synchronous Clocks with Offset
31.6.1.1
Synchronous Clocks with Offset Register Configuration
31.6.2
EPG Example: Serial Data Bit Stream (LSB first)
31.6.2.1
Serial Data Bit Stream (LSB first) Register Configuration
31.6.3
EPG Example: Serial Data Bit Stream (MSB first)
31.6.3.1
Serial Data Bit Stream (MSB first) Register Configuration
31.7
EPG Interrupt
31.8
Software
31.8.1
EPG Registers to Driverlib Functions
31.8.2
EPG Examples
31.8.2.1
EPG Generating Synchronous Clocks
31.8.2.2
EPG Generating Two Offset Clocks
31.8.2.3
EPG Generating Two Offset Clocks With SIGGEN
31.8.2.4
EPG Generate Serial Data
31.8.2.5
EPG Generate Serial Data Shift Mode
31.9
EPG Registers
31.9.1
EPG Base Address Table
31.9.2
EPG_REGS Registers
31.9.3
EPG_MUX_REGS Registers
32
Revision History
5.1.1
DCSM Related Collateral
Getting Started Materials
C2000 DCSM Security Tool Application Report
C2000 Unique Device Number Application Report
Enhancing Device Security by Using JTAGLOCK Feature Application Report
Secure BOOT On C2000 Device Application Report