SNLA426 june   2023 DS320PR1601 , DS320PR410

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 PCIe Gen3, Gen4, and Gen5 Loss Budget
  6. 3 Minimum Eye Width
  7. 4 Cross Talk Mitigation
  8. 5 Humidity and Temperature Insertion Loss
  9. 6 Critical Signals
  10. 7 General High-Speed Signal Routing
  11. 8 PCB Grain and Fiber Weave Selection
  12. 9 PCB Material Loss Budget
  13. 10High-Speed Signal Trace Impedance
  14. 11High-Speed Signal Trace Length Matching
  15. 12Differential Trace Routing Guidelines
  16. 13Differential-Inter-Pair Matching
  17. 14Intra-pair Length Matching
  18. 15Trace Bends
  19. 16Minimum Differential Trace-To-Trace Distance
  20. 17Serpentine Guidelines
  21. 18High-Speed Differential Signal Quick Rules
  22. 19High-Speed Differential Pair Reference Plane
  23. 20Via Staggering
  24. 21Via Stubs
  25. 22Via Pads
  26. 23Via Discontinuity Mitigation
  27. 24Back-Drill Stubs
  28. 25AC Coupling Capacitors Placement
  29. 26AC Coupling Capacitor Physical Placement
  30. 27Auxiliary Signal AC Match Termination
  31. 28Suggested PCB Stack-ups
  32. 29Summary
  33. 30References

9 PCB Material Loss Budget

The PCB material plays a large role in achieving optimum signal integrity. Table 9-1 shows insertion loss – SDD21 – of 1 inch of different board materials using different dielectric constants and loss tangents. Loss tangent (Df) or Dissipation Factor is a measure of signal attenuation as a signal propagates through a transmission line. This attenuation is due to the electromagnetic wave absorption in the dielectric material and is referred to as dielectric loss. As frequency increases, the dielectric loss also increases proportionally.

Common material choices for high-speed signal layers are Panasonic Megtron 6, Roger, and GETEK. TI has successfully utilized Panasonic Megtron 6 for a variety of high-speed board designs.

Table 9-1 1" Trace Loss Over Frequency for Various PCB Materials
Material Name εr (Dielectric Constant) Df (Loss Tangent) 1” SDD21 at 8GHz(dB) 1” SDD21 at 16GHz(dB)
Megtron 6 3.4 0.002 0.189 0.336
Roger 3.48 0.0037 0.251 0.411
GETEK 4.1 0.011 0.548 1.017
Nelco 4000-6 4.0 0.012 0.578 1.078
FR4 4.4 0.014 0.686 1.289
Tetra Functional FR4 4.1 0.022 0.961 1.844

Total insertion loss is calculated as follows:

Equation 1. 31.6 D i f f   I m p e d a n c e × ( W + T ) × ( f + 2.32 ε r × D f × f )
Zo is calculated as follows:
Equation 2. Z o = 87 ε r + 1.41 × L N 5.98 × H 0.8 × W + T

Note: Zo is designed to equal 85 Ω differential impedance, given this is the requirement for PCIe add-in-card applications.

  • ƒ = frequency (GHz)
  • εr = Dielectric Constant of material
  • Df = Loss tangent of material
  • W = Trace Width (mils)
  • T = Trace thickness (mils)
  • D = Trace edge-to-edge spacing (mils)
  • H = Distance to nearest reference plane (mils)

PCB loss is a fraction of the total channel loss; additional loss due to the device package, vias, connectors, and so on and also have to be considered. When there are multiple vias, reference plane changes, and connectors, the channel frequency response becomes complex. Each time the signal travels through a via, connector, or hits a package with similar parasitic, these affect signal reflections and loss differently. A complex multi-tap DFE must be utilized to track these changes and equalize the signal correctly. To summarize, it is best to minimize the number of vias, connectors, and optimize landing pads of the ASIC.

For high speed PCB layout design, low loss material such as Megtron 6 is used on just the top and bottom layers – where high-speed signals are routed. Please note, other than cost, using low loss materials typically causes a longer PCB fabrication time. Additionally, it can take a longer amount time to acquire lower loss PCB materials since these might not be widely used.