Do not place probe or test points on any high-speed differential signal.
Do not route high-speed traces under or near crystals, oscillators, clock signal generators, switching power regulators, mounting holes, magnetic devices, edge of the board, or ICs that use or duplicate clock signals.
After BGA breakout, keep high-speed differential signals clear of the PCIe device because high current transients produced during internal state transitions can be difficult to filter out.
When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an adjacent GND layer.
Make sure the high-speed differential signals are routed ≥ 5XW or 5XRPH – whichever is bigger - mils from the edge of the reference plane.
Make sure the high-speed differential signals are routed at least 4XRPH away from voids in the reference plane. This rule does not apply where SMD pads on high-speed differential signals are voided.
Maintain constant trace width after the PCIe device BGA escape to avoid impedance mismatches in the transmission lines.
To improve cross talk, follow ground-signal-ground signal routing and route all high-speed differential pairs together symmetrically and parallel to each other. Deviating from this requirement occurs naturally during package escape and when routing to connector pins. Trace deviations must be as short as possible – otherwise this can require trace width compensation. HFSS simulation can optimize trace width.
Crosstalk Between the Differential Signal Pairs: In devices that include multiple high-speed interfaces, avoiding crosstalk between various interfaces is important. To avoid crosstalk, make sure that each differential pair is not routed within 4-5 X RPH mils of another differential pair after package escape and before connector termination.