19 High-Speed Differential Pair Reference Plane

The entirety of any high-speed signal trace must maintain the same GND reference from origination to termination. If unable to maintain the same GND reference, via-stitch both GND planes together to make sure of continuous grounding and uniform impedance. Place stitching vias symmetrically within 50 mils (center- to-center, closer is better) of the signal transition vias.

For differential signals, the transmission line is formed by two traces and a reference plane. Good signal integrity depends on differential signals with controlled impedance. Controlled impedance is achieved by implementing optimized trace geometries and taking into account the dielectric constant and Loss Tangent of the board material you're working with. While the dielectric constant varies from board to board, the dielectric is constant within one board. Therefore, the impedance of a differential line is mostly dependent on the trace geometries and tolerances allowed at the PCB fab house. Impedance variance occurs based on the presence or absence of glass in a local portion of the PCB as noted earlier, but this poses issues at high speed (>3GHz Nyquist).

High-speed signals must be routed over a solid reference plane and not across a plane split or a void in the reference plane unless absolutely necessary. TI does not recommend high-speed signal references to power planes.

Routing across a plane split or a void in the reference plane forces return high-frequency current to flow around the split or void. This can result in the following conditions:

• Excess radiated emissions from an unbalanced current flow
• Delays in signal propagation due to increased series inductance
• Interference with adjacent signals
• Degraded signal integrity (that is, more jitter and reduced signal amplitude)

For examples of incorrect and correct plane void routing, see Figure 19-1 and Figure 19-2 for incorrect and correct trace routing, respectively.

Note, when a trace goes around the void, we need to make sure we have at least 4 times reference plane height to maintain target differential impedance.

Figure 19-1 Incorrect Plane Void Routing

Figure 19-2 Correct Plane Voiding

If routing over a plane-split is completely unavoidable, place stitching capacitors across the split to provide a return path for the high-frequency current. Stitching capacitors minimize the current loop area and any impedance discontinuity created by crossing the split. The capacitors must be 1 µF or lower and placed as close as possible to the plane crossing. For examples of correct stitch capacitor placement, see Figure 19-3.

Figure 19-3 Stitching Capacitor over Plane Split

When planning a PCB stack-up, make sure that planes that do not reference each other are not overlapped because this produces unwanted capacitance between the overlapping areas. To see an example of how this capacitance can pass RF emissions from one plane to the other, see Figure 19-4.

Figure 19-4 Passed Capacitance Examples