SNLA426 june   2023 DS320PR1601 , DS320PR410

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 PCIe Gen3, Gen4, and Gen5 Loss Budget
  6. 3 Minimum Eye Width
  7. 4 Cross Talk Mitigation
  8. 5 Humidity and Temperature Insertion Loss
  9. 6 Critical Signals
  10. 7 General High-Speed Signal Routing
  11. 8 PCB Grain and Fiber Weave Selection
  12. 9 PCB Material Loss Budget
  13. 10High-Speed Signal Trace Impedance
  14. 11High-Speed Signal Trace Length Matching
  15. 12Differential Trace Routing Guidelines
  16. 13Differential-Inter-Pair Matching
  17. 14Intra-pair Length Matching
  18. 15Trace Bends
  19. 16Minimum Differential Trace-To-Trace Distance
  20. 17Serpentine Guidelines
  21. 18High-Speed Differential Signal Quick Rules
  22. 19High-Speed Differential Pair Reference Plane
  23. 20Via Staggering
  24. 21Via Stubs
  25. 22Via Pads
  26. 23Via Discontinuity Mitigation
  27. 24Back-Drill Stubs
  28. 25AC Coupling Capacitors Placement
  29. 26AC Coupling Capacitor Physical Placement
  30. 27Auxiliary Signal AC Match Termination
  31. 28Suggested PCB Stack-ups
  32. 29Summary
  33. 30References

8 PCB Grain and Fiber Weave Selection

When routing differential signals across common PCB materials, each trace experiences different dielectric constants and corresponding signal velocities due to the differences in static permittivity (εr) of the fiberglass weave (εr is approximately 6) and epoxy (εr is approximately 3) that comprise a PCB. Differences between εr and loss tangent (Df) are caused by holes or openings within the fiber glass laminate. These differences cause resonance or anti-resonance in return loss or the insertion loss of the transmission media at different frequencies across the signal bandwidth.

A signal travels faster when εr is lower; therefore, an intra-pair skew can develop if a signal in a differential pair travels over a higher ratio of fiberglass or epoxy than the companion signal does. This intra-pair skew starts appearing on SDD12 and SDD22 at 2GHz and higher. This skew between the differential signals can significantly degrade the differential eye diagram as presented to the receiver, causing significant duty cycle distortion, AC common-mode voltage noise, and EMI issues. The extent of this problem will depend on the data rate, the length of the traces, the trace geometries, the type of fiberglass weave used, and the alignment of the traces to the weave pattern of a PCB. Problems from fiber weave alignment vary from board to board. This variance makes issues difficult to diagnose.

εr typically ranges from 2.5 to 4.5 and varies with frequency – decreases as frequency increases. Df is a measurement of material power dissipation or the degree of signal attenuation and typically ranges from 0.02 to 0.001 for ultra-low loss materials. Smaller values of Df result in lower signal attenuation, thus a low Df is desirable for high speed applications such as PCIe.

Figure 8-1 and Figure 8-2 show the two most common methods to minimize the impact of PCB fiber weave in a board design. The goal of each method is to ensure that both signals of the differential pair will share a relatively common across the length of the pair routing.

The entirety of the signaling image plane is rotated 10° to 35° in relation to the underlying PCB fiber weave. The PCB manufacturer can affect this rotation without making changes to the PCB layout database as shown in Figure 8-1.

GUID-20230511-SS0I-RKDX-BCRC-HKQB892K67BB-low.svgFigure 8-1 Rotation of the PCB Image

The high-speed differential signals are routed in a zig-zag fashion across the PCB as shown in Figure 8-2

GUID-20230511-SS0I-TQ1M-VG6P-3HX1F4TGFTP6-low.svgFigure 8-2 Zig-Zag Routing

Because the ratio of fiberglass to epoxy is the primary contributor to the εr disparity, choose a PCB style with a tighter weave, less epoxy, and greater εr uniformity across longer trace lengths. Before sending the design out for fabrication, specify a PCB style that can best accommodate high-speed signals.