SNLA426 june   2023 DS320PR1601 , DS320PR410

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 PCIe Gen3, Gen4, and Gen5 Loss Budget
  6. 3 Minimum Eye Width
  7. 4 Cross Talk Mitigation
  8. 5 Humidity and Temperature Insertion Loss
  9. 6 Critical Signals
  10. 7 General High-Speed Signal Routing
  11. 8 PCB Grain and Fiber Weave Selection
  12. 9 PCB Material Loss Budget
  13. 10High-Speed Signal Trace Impedance
  14. 11High-Speed Signal Trace Length Matching
  15. 12Differential Trace Routing Guidelines
  16. 13Differential-Inter-Pair Matching
  17. 14Intra-pair Length Matching
  18. 15Trace Bends
  19. 16Minimum Differential Trace-To-Trace Distance
  20. 17Serpentine Guidelines
  21. 18High-Speed Differential Signal Quick Rules
  22. 19High-Speed Differential Pair Reference Plane
  23. 20Via Staggering
  24. 21Via Stubs
  25. 22Via Pads
  26. 23Via Discontinuity Mitigation
  27. 24Back-Drill Stubs
  28. 25AC Coupling Capacitors Placement
  29. 26AC Coupling Capacitor Physical Placement
  30. 27Auxiliary Signal AC Match Termination
  31. 28Suggested PCB Stack-ups
  32. 29Summary
  33. 30References

2 PCIe Gen3, Gen4, and Gen5 Loss Budget

PCIe Gen5 and lower rates use differential AC coupled transmission lines. Polarity inversion is allowed since NRZ data is used. There is on-chip termination that activates after the Rx detect process is asserted on both inputs and outputs to facilitate signal integrity. More importantly, PCIe Gen3 through Gen5 uses link training, allowing both TX and RX link equalization.

Before we get started discussing PCB layout guidelines, let’s start with PCIe overall design considerations. Table 2-1 outlines the loss budget (dB) for PCIe Gen3 through Gen5, while Table 2-2 outlines the PCIe eye opening requirements for Gen3 through Gen5.

Table 2-1 PCIe Gen3 through Gen5 Loss Budget
Loss BreakdownGen3 (dB)Gen4 (dB)Gen5 (dB)
CPU Package3.559.0
System Board Trace (9-inch trace with high-loss material)131416
CEM Connector0.50.51.5
4” Add-In-Card6.58.59.5
Total System Loss23.52836
Cross Talk MitigationNegligible<24-5
Temp/Humidity Loss--2-3
Table 2-2 PCIe Gen3 through Gen5 Eye Opening
Eye OpeningGen3Gen4Gen5
Extrapolated Eye Height after EQ25 mV15 ± 1.5mV15 ± 1.5mV
Minimum Eye Width after EQ0.3UI (37.5ps)0.3UI (18.75 ± 0.55ps)0.3UI (9.375 ± 0.5ps)