SLUSAM9E July   2011  – April 2020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Internal Power Control (Startup and Shutdown)
    7. 7.7  3.3-V Voltage Regulator
    8. 7.8  Voltage Reference
    9. 7.9  Cell Voltage Amplifier
    10. 7.10 Current Sense Amplifier
    11. 7.11 Overcurrent Comparator
    12. 7.12 Internal Temperature Measurement
    13. 7.13 Cell Balancing and Open Cell Detection
    14. 7.14 I2C Compatible Interface
    15. 7.15 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Internal LDO Voltage Regulator
      2. 8.3.2 ADC Interface
        1. 8.3.2.1 Reference Voltage
          1. 8.3.2.1.1 Host ADC Calibration
        2. 8.3.2.2 Cell Voltage Monitoring
          1. 8.3.2.2.1 Cell Amplifier Headroom Under Extreme Cell Imbalance
          2. 8.3.2.2.2 Cell Amplifier Headroom Under BAT Voltage Drop
        3. 8.3.2.3 Current Monitoring
        4. 8.3.2.4 Overcurrent Monitoring
        5. 8.3.2.5 Temperature Monitoring
          1. 8.3.2.5.1 Internal Temperature Monitoring
      3. 8.3.3 Cell Balancing and Open Cell Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 POWER ON RESET (POR)
        2. 8.4.1.2 STANDBY
        3. 8.4.1.3 SLEEP
    5. 8.5 Programming
      1. 8.5.1 Host Interface
        1. 8.5.1.1 I2C Addressing
        2. 8.5.1.2 Bus Write Command to BQ76925
        3. 8.5.1.3 Bus Read Command from BQ76925 Device
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 Voltage, Current, and Temperature Outputs
        2. 9.1.1.2 Power Management
        3. 9.1.1.3 Low Dropout (LDO) Regulator
        4. 9.1.1.4 Input Filters
        5. 9.1.1.5 Output Filters
      2. 9.1.2 Cell Balancing
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.6 Register Maps

Address Name Access D7 D6 D5 D4 D3 D2 D1 D0
0x00 STATUS R/W ALERT CRC_ERR POR
0x01 CELL_CTL R/W VCOUT_SEL CELL_SEL
0x02 BAL_CTL R/W BAL_6 BAL_5 BAL_4 BAL_3 BAL_2 BAL_1
0x03 CONFIG_1 R/W I_THRESH I_COMP_POL I_AMP_CAL I_GAIN
0x04 CONFIG_2 R/W CRC_EN REF_SEL
0x05 POWER_CTL R/W SLEEP SLEEP_DIS I_COMP_EN I_AMP_EN VC_AMP_EN VTB_EN REF_EN
0x06 Reserved R/W
0x07 CHIP_ID RO CHIP_ID
0x08 – 0x0F Reserved R/W
0x10 VREF_CAL EEPROM VREF_OFFSET_CORR VREF_GAIN_CORR
0x11 VC1_CAL EEPROM VC1_OFFSET_CORR VC1_GAIN_CORR
0x12 VC2_CAL EEPROM VC2_OFFSET_CORR VC2_GAIN_CORR
0x13 VC3_CAL EEPROM VC3_OFFSET_CORR VC3_GAIN_CORR
0x14 VC4_CAL EEPROM VC4_OFFSET_CORR VC4_GAIN_CORR
0x15 VC5_CAL EEPROM VC5_OFFSET_CORR VC5_GAIN_CORR
0x16 VC6_CAL EEPROM VC6_OFFSET_CORR VC6_GAIN_CORR
0x17 VC_CAL_EXT_1 EEPROM VC1_OC_4 VC1_GC_4 VC2_OC_4 VC2_GC_4
0x18 VC_CAL_EXT_2 EEPROM VC3_OC_4 VC3_GC_4 VC4_OC_4 VC4_GC_4 VC5_OC_4 VC5_GC_4 VC6_OC_4 VC6_GC_4
0x10 – 0x1A Reserved EEPROM
0x1B VREF_CAL_EXT EEPROM 1 VREF_OC_5 VREF_OC_4 VREF_GC_4
0x1C – 0x1F Reserved EEPROM