SLUSAM9E July   2011  – April 2020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Internal Power Control (Startup and Shutdown)
    7. 7.7  3.3-V Voltage Regulator
    8. 7.8  Voltage Reference
    9. 7.9  Cell Voltage Amplifier
    10. 7.10 Current Sense Amplifier
    11. 7.11 Overcurrent Comparator
    12. 7.12 Internal Temperature Measurement
    13. 7.13 Cell Balancing and Open Cell Detection
    14. 7.14 I2C Compatible Interface
    15. 7.15 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Internal LDO Voltage Regulator
      2. 8.3.2 ADC Interface
        1. 8.3.2.1 Reference Voltage
          1. 8.3.2.1.1 Host ADC Calibration
        2. 8.3.2.2 Cell Voltage Monitoring
          1. 8.3.2.2.1 Cell Amplifier Headroom Under Extreme Cell Imbalance
          2. 8.3.2.2.2 Cell Amplifier Headroom Under BAT Voltage Drop
        3. 8.3.2.3 Current Monitoring
        4. 8.3.2.4 Overcurrent Monitoring
        5. 8.3.2.5 Temperature Monitoring
          1. 8.3.2.5.1 Internal Temperature Monitoring
      3. 8.3.3 Cell Balancing and Open Cell Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 POWER ON RESET (POR)
        2. 8.4.1.2 STANDBY
        3. 8.4.1.3 SLEEP
    5. 8.5 Programming
      1. 8.5.1 Host Interface
        1. 8.5.1.1 I2C Addressing
        2. 8.5.1.2 Bus Write Command to BQ76925
        3. 8.5.1.3 Bus Read Command from BQ76925 Device
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 Voltage, Current, and Temperature Outputs
        2. 9.1.1.2 Power Management
        3. 9.1.1.3 Low Dropout (LDO) Regulator
        4. 9.1.1.4 Input Filters
        5. 9.1.1.5 Output Filters
      2. 9.1.2 Cell Balancing
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.6.1 Register Descriptions

Table 5. STATUS Register

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x00 STATUS R/W ALERT CRC_ERR POR
Defaults: 0 0 0 0 0 0 0 1

ALERT: Over-current alert. Reflects state of the over-current comparator. ‘1’ = over-current.

CRC_ERR: CRC error status. Updated on every I2C write packet when CRC_EN = ‘1’. ‘1’ = CRC error.

POR: Power on reset flag. Set on each power-up and wake-up from sleep. May be cleared by writing with ‘0’.

Table 6. CELL_CTL

Address Name Type D7(1) D6 D5 D4 D3 D2 D1 D0
0x01 CELL_CTL R/W VCOUT_SEL CELL_SEL
Defaults: 0 0 0 0 0
(1) This bit must be kept = 0

VCOUT_SEL: VCOUT MUX select. Selects the VCOUT pin function as follows.

Table 7. VCOUT Pin Functions

VCOUT_SEL VCOUT
0 0 VSS
0 1 VCn (n determined by CELL_SEL)
1 0 VREF × 0.5
1 1 VREF × 0.85

CELL_SEL: Cell select. Selects the VCn input for output on VCOUT when VCOUT_SEL = ‘01’.

Table 8. Cell Selection

VCOUT_SEL CELL_SEL VCOUT
0 1 0 0 0 VC1
0 1 0 0 1 VC2
0 1 0 1 0 VC3
0 1 0 1 1 VC4
0 1 1 0 0 VC5
0 1 1 0 1 VC6
0 1 1 1 0 VTEMP,INT
0 1 1 1 1 Hi-Z

Table 9. BAL_CTL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x02 BAL_CTL R/W BAL_6 BAL_5 BAL_4 BAL_3 BAL_2 BAL_1
Defaults: 0 0 0 0 0 0 0 0

BAL_n: Balance control for cell n. When set, turns on balancing transistor for cell n. Setting of two adjacent balance controls is not permitted. If two adjacent balance controls are set, neither cell balancing transistor will be turned on. However, the BAL_n bits will retain their values.

Table 10. CONFIG_1

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x03 CONFIG_1 R/W I_THRESH I_COMP_POL I_AMP_CAL I_GAIN
Defaults: 0 0 0 0 0

I_THRESH: Current comparator threshold. Sets the threshold of the current comparator as follows:

Table 11. Current Comparator Threshold

I_THRESH Comparator Threshold
0x0 25 mV
0x1 50 mV
0x2 75 mV
0x3 100 mV
0x4 125 mV
0x5 150 mV
0x6 175 mV
0x7 200 mV
0x8 225 mV
0x9 250 mV
0xA 275 mV
0xB 300 mV
0xC 325 mV
0xD 350 mV
0xE 375 mV
0xF 400 mV

I_COMP_POL: Current comparator polarity select. When ‘0’, trips on discharge current (SENSEP > SENSEN). When ‘1’, trips on charge current (SENSEP < SENSEN).

I_AMP_CAL: Current amplifier calibration. When ‘0’, current amplifier reports SENSEN with respect to VSS. When ‘1’, current amplifier reports SENSEP with respect to VSS. This bit can be used for offset cancellation as described under OPERATIONAL OVERVIEW.

I_GAIN: Current amplifier gain. Sets the nominal gain of the current amplifier as follows.

Table 12. Nominal Gain of the Current Amplifier

I_GAIN Current amp gain
0 4
1 8

Table 13. CONFIG_2

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x04 CONFIG_2 R/W CRC_EN REF_SEL
Defaults: 0 0 0 0 0 0 0 0

CRC_EN: CRC enable. Enables CRC comparison on write. When ‘1’, CRC is enabled. CRC on read is always enabled but is optional for Host.

REF_SEL: Reference voltage selection. Sets reference voltage output on VREF pin, cell-voltage amplifier gain and VIOUT output range.

Table 14. Reference Voltage Selection

REF_SEL VREF (V) VCOUT Gain VIOUT Output Range (V)
0 1.5 0.3 0.25 – 1.25
1 3.0 0.6 0.5 – 2.5

Table 15. POWER_CTL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x05 POWER_CTL R/W SLEEP SLEEP_DIS I_COMP_EN I_AMP_EN VC_AMP_EN VTB_EN REF_EN
Defaults: 0 0 0 0 0 0 0 0

SLEEP: Sleep control. Set to ‘1’ to put device to sleep

SLEEP_DIS: Sleep mode disable. When ‘1’, disables the sleep mode.

I_COMP_EN: Current comparator enable. When ‘1’, comparator is enabled. Disable to save power.

I_AMP_EN: Current amplifier enable. When ‘1’, current amplifier is enabled. Disable to save power.

VC_AMP_EN: Cell amplifier enable. When ‘1’, cell amplifier is enabled. Disable to save power.

VTB_EN: Thermistor bias enable. When ‘1’, the VTB pin is internally switched to the V3P3 voltage.

REF_EN: Voltage reference enable. When ‘1’, the 1.5 / 3.0 V reference is enabled. Disable to save power

Table 16. CHIP_ID

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x07 CHIP_ID RO CHIP_ID
Defaults: 0x10

CHIP_ID: Silicon version identifier.

Table 17. VREF_CAL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x10 VREF_CAL EEPROM VREF_OFFSET_CORR VREF_GAIN_CORR

VREF_OFFSET_CORR: Lower 4 bits of offset-correction factor for reference output. The complete offset-correction factor is obtained by concatenating this value with the the two most significant bits VREF_OC_5 and VREF_OC_4, which are stored in the VREF_CAL_EXT register. The final value is a 6-bit signed 2’s complement number in the range –32 to +31 with a value of 1 mV per LSB. See description of usage in Detailed Description.

VREF_GAIN_CORR: Lower 4 bits of gain correction factor for reference output. The complete gain correction factor is obtained by concatenating this value with the most significant bit VREF_GC_4, which is stored in the VREF_CAL_EXT register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 0.1% per lsb. See description of usage in Detailed Description.

Table 18. VC1_CAL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x11 VC1_CAL EEPROM VC1_OFFSET_CORR VC1_GAIN_CORR

VC1_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 1 translation. The complete offset correction factor is obtained by concatenating this value with the most significant bit VC1_OC_4, which is stored in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a value of 1 mV per lsb. See description of usage in Detailed Description.

VC1_GAIN_CORR: Lower 4 bits of gain correction factor for cell 1 translation. The complete gain correction factor is obtained by concatenating this value with the most significant bit VC1_GC_4, which is stored in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a value of 0.1% per lsb. See description of usage in Detailed Description.

Table 19. VC2_CAL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x12 VC2_CAL EEPROM VC2_OFFSET_CORR VC2_GAIN_CORR

VC2_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 2 translation. The complete offset correction factor is obtained by concatenating this value with the most significant bit VC2_OC_4, which is stored in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 1 mV per LSB. See description of usage in See description of usage in Detailed Description.

VC2_GAIN_CORR: Lower 4 bits of gain correction factor for cell 2 translation. The complete gain correction factor is obtained by concatenating this value with the most significant bit VC2_GC_4, which is stored in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 0.1% per LSB. See description of usage in Detailed Description.

Table 20. VC3_CAL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x13 VC3_CAL EEPROM VC3_OFFSET_CORR VC3_GAIN_CORR

VC3_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 3 translation. The complete offset correction factor is obtained by concatenating this value with the most significant bit VC3_OC_4, which is stored in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 1 mV per lsb. See description of usage in Detailed Description.

VC3_GAIN_CORR: Lower 4 bits of gain correction factor for cell 3 translation. The complete gain correction factor is obtained by concatenating this value with the most significant bit VC3_GC_4, which is stored in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 0.1% per lsb. See description of usage in Detailed Description.

Table 21. VC4_CAL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x14 VC4_CAL EEPROM VC4_OFFSET_CORR VC4_GAIN_CORR

VC4_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 4 translation. The complete offset correction factor is obtained by concatenating this value with the most significant bit VC4_OC_4, which is stored in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 1 mV per lsb. See description of usage in Detailed Description.

VC4_GAIN_CORR: Lower 4 bits of gain correction factor for cell 4 translation. The complete gain correction factor is obtained by concatenating this value with the most significant bit VC4_GC_4, which is stored in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 0.1% per lsb. See description of usage in Detailed Description.

Table 22. VC5_CAL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x15 VC5_CAL EEPROM VC5_OFFSET_CORR VC5_GAIN_CORR

VC5_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 5 translation. The complete offset correction factor is obtained by concatenating this value with the most significant bit VC5_OC_4, which is stored in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 1 mV per LSB. See description of usage in Detailed Description.

VC5_GAIN_CORR: Lower 4 bits of gain correction factor for cell 5 translation. The complete gain correction factor is obtained by concatenating this value with the most significant bit VC5_GC_4, which is stored in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 0.1% per LSB. See description of usage in Detailed Description.

Table 23. VC6_CAL

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x16 VC6_CAL EEPROM VC6_OFFSET_CORR VC6_GAIN_CORR

VC6_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 6 translation. The complete offset correction factor is obtained by concatenating this value with the most significant bit VC6_OC_4, which is stored in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 1 mV per LSB. See description of usage in Detailed Description.

VC6_GAIN_CORR: Lower 4 bits of gain correction factor for cell 6 translation. The complete gain correction factor is obtained by concatenating this value with the most significant bit VC6_GC_4, which is stored in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a value of 0.1% per LSB. See description of usage in Detailed Description.

Table 24. VC_CAL_EXT_1

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x17 VC_CAL_EXT_1 EEPROM VC1_OC_4 VC1_GC_4 VC2_OC_4 VC2_GC_4

VC1_OC_4: Most significant bit of offset correction factor for cell 1 translation. See Table 18 register description for details.

VC1_GC_4: Most significant bit of gain correction factor for cell 1 translation. See Table 18 register description for details.

VC2_OC_4: Most significant bit of offset correction factor for cell 2 translation. See Table 19 register description for details.

VC2_GC_4: Most significant bit of gain correction factor for cell 2 translation. See Table 19 register description for details.

Table 25. VC_CAL_EXT_2

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x18 VC_CAL_EXT_2 EEPROM VC3_OC_4 VC3_GC_4 VC4_OC_4 VC4_GC_4 VC5_OC_4 VC5_GC_4 VC6_OC_4 VC6_GC4

VC3_OC_4: Most significant bit of offset correction factor for cell 3 translation. See Table 20 register description for details.

VC3_GC_4: Most significant bit of gain correction factor for cell 3 translation. See Table 20 register description for details.

VC4_OC_4: Most significant bit of offset correction factor for cell 4 translation. See Table 21 register description for details.

VC4_GC_4: Most significant bit of gain correction factor for cell 4 translation. See Table 21 register description for details.

VC5_OC_4: Most significant bit of offset correction factor for cell 5 translation. See Table 22 register description for details.

VC5_GC_4: Most significant bit of gain correction factor for cell 5 translation. See Table 22 register description for details.

VC6_OC_4: Most significant bit of offset correction factor for cell 6 translation. See Table 23 register description for details.

VC6_GC_4: Most significant bit of gain correction factor for cell 6 translation. See Table 23 register description for details.

Table 26. VREF_CAL_EXT

Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x1B VREF_CAL_EXT EEPROM 1 VREF_OC_5 VCREF_OC_4 VREF_GC4

VREF_OC_5: Most significant bit of offset correction factor for reference output. See Table 17 register description for details.

VREF_OC_4: Next most significant bit of offset correction factor for reference output. See Table 17 register description for details.

VREF_GC_4: Most significant bit of gain correction factor for reference output. See Table 17 register description for details.