ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a general register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | EN_HIGH_ADDRS | X | READOUT | ||||
W-0 | W-0 | W-0 | W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D5 | X | W | 0 | Don't care bits |
D4 | EN_HIGH_ADDRS | W | 0 | Register F0h access 0 = Disables access to register F0h (default) 1 = Enables access to register F0h |
D3-D1 | X | W | 0 | Don't care bits |
D0 | READOUT | W | 0 | Register mode readout 0 = Normal operation (default) 1 = Register mode readout |