ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
Aperture delay | 4 | ns | |||||
Aperture delay matching(2)(3) | Between the two channels of the same device | ±175 | ps | ||||
Aperture delay variation | Between two devices at the same temperature and LVDD supply | 2.5 | ns | ||||
Aperture jitter (RMS) | 320 | fs | |||||
Wakeup time | Time to valid data after coming out of partial power-down mode |
5 | 50 | µs | |||
Time to valid data after coming out of global power-down mode |
100 | 500 | µs | ||||
ADC latency | One-lane LVDS output interface | 11 | Clock cycles | ||||
Two-lane LVDS output interface | 15 | Clock cycles | |||||
tsu | Data setup time | Data valid to zero crossing of LCLKP, 80 MSPS, two-lane LVDS |
0.61 | ns | |||
th | Data hold time(4) | Zero crossing of LCLKP to data becoming invalid, 80 MSPS, two-lane LVDS |
0.74 | ns | |||
tp | Clock propagation delay | Input clock rising edge crossover to frame clock rising edge crossover, two-lane LVDS for 10 ≤ ƒS ≤ 80 MSPS |
(11 / 12) × tS + td |
ns | |||
Input clock rising edge crossover to frame clock rising edge crossover, one-lane LVDS for 10 ≤ ƒS ≤ 65 MSPS |
(9 / 12) × tS + td |
ns | |||||
td | Delay time | 6.8 | 9 | 11.8 | ns | ||
LVDS bit clock duty cycle | Differential clock duty cycle (LCLKP – LCLKM) | 50 | % | ||||
tf | Data fall time | Rise time measured from –100 mV to 100 mV, 10 MSPS ≤ sampling frequency ≤ 80 MSPS |
0.2 | ns | |||
tr | Data rise time | Rise time measured from –100 mV to 100 mV, 10 MSPS ≤ sampling frequency ≤ 80 MSPS |
0.2 | ns | |||
tr(CLK) | Output clock rise time | Rise time measured from –100 mV to 100 mV, 10 MSPS ≤ sampling frequency ≤ 80 MSPS |
0.18 | ns | |||
tf(CLK) | Output clock fall time | Rise time measured from –100 mV to 100 mV, 10 MSPS ≤ sampling frequency ≤ 80 MSPS |
0.18 | ns |