ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
V(AVDD) | Analog supply voltage | 1.7 | 1.8 | 1.9 | V | |
V(LVDD) | Digital supply voltage | 1.7 | 1.8 | 1.9 | V | |
VID | Differential input voltage | 2 | VPP | |||
VIC | Input common-mode voltage | VIC ± 50 | mV | |||
Input clock sample rate | Two-lane LVDS interface | 10 | 80 | MSPS | ||
One-lane LVDS interface | 10 | 50 | MSPS | |||
(VCLKP – VCLKM) | Input clock amplitude differential | Sine wave, ac-coupled | 1.5 | VPP | ||
LVPECL, ac-coupled | 1.6 | VPP | ||||
LVDS, ac-coupled | 0.7 | VPP | ||||
LVCMOS, single-ended, ac-coupled | 3.3 | V | ||||
Duty cycle | 35% | 50% | 65% | |||
CLOAD | Maximum external capacitance from each output pin to DRGND | 5 | pF | |||
RLOAD | Differential resistance between LVDS output pairs (LVDS mode) | 100 | Ω | |||
TA | Operating free-air | –40 | 105 | °C |