ZHCSKI6T January   2006  – December 2023 TPS737

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Noise
      2. 6.3.2 Internal Current Limit
      3. 6.3.3 Enable Pin and Shutdown
      4. 6.3.4 Reverse Current
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Dropout Voltage
        3. 7.2.2.3 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Power Dissipation
        2. 7.5.1.2 Thermal Protection
        3. 7.5.1.3 Estimating Junction Temperature
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DCQ|6
  • DRV|6
  • DRB|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.3.1 Output Noise

A precision band-gap reference is used to generate the internal reference voltage, Vref. This reference is the dominant noise source within the TPS737xx and generates approximately 32 μVRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by:

Equation 1. GUID-DFC3B311-9E8D-48BD-B6FE-B0E0473ADD69-low.gif

Because the value of VR is 1.2 V, this relationship reduces to:

Equation 2. GUID-C2047517-2E10-4BE5-980D-1EEF125A2849-low.gif

for the case of no CNR.

An internal 27-kΩ resistor in series with the noise-reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise-reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF, the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship:

Equation 3. GUID-CA21C66A-E678-4EA2-9497-65C6243B0539-low.gif

for CNR = 10 nF.

This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section.

The TPS73701 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient performance. Limit this capacitor to 0.1 µF.

The TPS737 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass transistor above VOUT. The charge pump generates approximately 250 μV of switching noise at approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT.