ZHCSG04F january   2017  – may 2023 TPS65235-1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short-Circuit Protection, Hiccup, and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Audio Noise Rejection
      10. 7.3.10 Disable and Enable
      11. 7.3.11 Component Selection
        1. 7.3.11.1 Boost Inductor
        2. 7.3.11.2 Capacitor Selection
        3. 7.3.11.3 Surge Components
        4. 7.3.11.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235-1 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00) [reset = 0x08]
      2. 7.6.2 Control Register 2 (address = 0x01) [reset = 0x09]
      3. 7.6.3 Status Register (address = 0x02) [reset = 0x29]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DiSEqc1.x Support
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DiSEqc2.x Support
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方产品免责声明
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.2 Control Register 2 (address = 0x01) [reset = 0x09]

Figure 7-13 Control Register 2
76543210
TONEAMPTIMERISWFSETENDOUTMODETONE_AUTOTONE_TRANS
R/W-0bR/W-0bR/W-0bR/W-0bR/W-1bR/W-0bR/W-0bR/W-1b
Table 7-6 Control Register 2
BitFieldTypeResetDescription
7TONEAMPR/W0b

0b = 22-kHz tone amplitude is 650 mV (typ)

1b = 22-kHz tone amplitude is 750 mV (typ)

6TIMERR/W0b

0b = Hiccup ON time set to 4 ms and OFF time set to 128 ms

1b = Hiccup ON time set to 8 ms and OFF time set to 256 ms

5ISWR/W0b

0b = Boost switch peak current limit set to 3 × IOCP + 0.8 A

1b = Boost switch peak current limit set to 5 × IOCP + 0.8 A

4FSETR/W0b

0b = 1-MHz switching frequency

1b = 500-kHz switching frequency

3ENR/W1b

0b = LNB output disabled

1b = LNB output voltage Enabled

2DOUTMODER/W0b

0b = DOUT is kept to low when DIN has the tone input

1b = Reserved, cannot set to 1b

1TONE_AUTOR/W0b

0b = GDR (External bypass FET control) is controlled by TONE_TRANS

1b = GDR (External bypass FET control) is automatically controlled by 22-kHz tones transmit

0TONE_TRANSR/W1b

0b = GDR output with VLNB voltage for tone receive. Bypass FET is OFF for tone receiving from satellite

1b = GDR output with VCP voltage. Bypass FET is ON for tone transmit from TPS65235-1

Table 7-7 22-kHz Tone Receive Mode Selection
TONE_AUTO TONE_TRANS BYPASS FET
0b 0b OFF
0b 1b ON
1b x Auto Detect

The TPS65235-1 has full range of diagnostic flags for operation and debug. Processor can read the status register to check the error conditions. After the error happens, the flags are changed, once the errors are gone, the flags are set back without I2C access.

If the TSD and OCP flags are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to processor. After TSD and OCP are set to 1b, the FAULT pin logic is latched to low, processor must read this status register to release the fault conditions.