ZHCSG62A March   2017  – May 2017 TPD2S703-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      USB 2.0 端口提供电池短路和 IEC ESD 保护
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC Specification
    3. 6.3  ESD Ratings—IEC Specification
    4. 6.4  ESD Ratings—ISO Specification
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Thermal Information
    7. 6.7  Electrical Characteristics
    8. 6.8  Power Supply and Supply Current Consumption Chracteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OVP Operation
      2. 8.3.2 OVP Threshold
      3. 8.3.3 D± Clamping Voltage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Operation
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VREF Operation
          1. 9.2.2.1.1 Mode 0
          2. 9.2.2.1.2 Mode 1
        2. 9.2.2.2 Mode 1 Enable Timing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VPWR Path
    2. 10.2 VREF Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.2.2.2 Mode 1 Enable Timing

In Mode 1, when the TPD2S703-Q1 is disabled, the output regulator is disabled, leading VREF to discharge to 0 V through RTOP and RBOT. It is desired for VREF to be at 0 V when the device is disabled to minimize the clamping voltage during a power disabled Short-to-Battery or ESD event. If VREF is at 0 V, this holds D± near ground during these fault events.

When enabling the TPD2S703-Q1, VREF is quickly charged up to insure a quick turnon time of the Data FETs. Data FET turnon is gated by VREF reaching 80% of its final voltage plus 150 µs to insure a proper OVP threshold is set before passing data. This prevents false OVPs due to normal operation. Because Data FET turnon is gated by charging the VREF clamping capacitor, the size of the capacitor influences the turnon time of the Data switches. The TPD2S703-Q1’s internal regulator uses a constant current source to quickly charge the VREF clamping capacitor, so the charging time of CVREF can easily be calculated with Equation 6.

Equation 6. TPD2S703-Q1 Equation_2.gif

Where CVREF is the clamping capacitance on VREF, VREFFINAL is the final value VREF is set to, and ICHG_VREF = 22 mA (typical). If VREF = 1 V, 0.8 is used in the above equation because 80% of VREF is the amount of time that gates the turnon of the Data FETs. Once tCHG_CVREF is calculated, the typical turnon time of the Data FETs can be calculated from Equation 7.

Equation 7. TPD2S703-Q1 Mode_Enable_Equation_4.gif