ZHCSG62A March   2017  – May 2017 TPD2S703-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      USB 2.0 端口提供电池短路和 IEC ESD 保护
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC Specification
    3. 6.3  ESD Ratings—IEC Specification
    4. 6.4  ESD Ratings—ISO Specification
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Thermal Information
    7. 6.7  Electrical Characteristics
    8. 6.8  Power Supply and Supply Current Consumption Chracteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OVP Operation
      2. 8.3.2 OVP Threshold
      3. 8.3.3 D± Clamping Voltage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Operation
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VREF Operation
          1. 9.2.2.1.1 Mode 0
          2. 9.2.2.1.2 Mode 1
        2. 9.2.2.2 Mode 1 Enable Timing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VPWR Path
    2. 10.2 VREF Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.1 OVP Operation

When the VD+, or VD– voltages rise above VOVP, the internal nFET switches are turned off, protecting the transceiver from overvoltage conditions. The response is very rapid, with the FET switches turning off in less than 1 µs. Before the OVP condition, the FLT pin is High-Z, and is pulled HIGH via an external resistor to indicate there is no fault. Once the OVP condition occurs, the FLT pin is asserted LOW. When the VD+, or VD– voltages returns below VOVP – VHYS-OVP, the nFET switches are turned on again. When the OVP condition is cleared and the nFETs are completely turned on, the FLT is reset to high-Z.