ZHCSFY1F December   2016  – April 2024 TDP158

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply
    6. 5.6  Electrical Characteristics, Differential Input
    7. 5.7  Electrical Characteristics, TMDS Differential Output
    8. 5.8  Electrical Characteristics, DDC, I2C, HPD, and ARC
    9. 5.9  Electrical Characteristics, TMDS Differential Output in DP-Mode
    10. 5.10 Switching Characteristics, TMDS
    11. 5.11 Switching Characteristics, HPD
    12. 5.12 Switching Characteristics, DDC and I2C
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reset Implementation
      2. 7.3.2  Operation Timing
      3. 7.3.3  Lane Control
      4. 7.3.4  Swap
      5. 7.3.5  Main Link Inputs
      6. 7.3.6  Receiver Equalizer
      7. 7.3.7  Input Signal Detect Block
      8. 7.3.8  Transmitter Impedance Control
      9. 7.3.9  TMDS Outputs
      10. 7.3.10 Slew Rate Control
      11. 7.3.11 Pre-Emphasis
      12. 7.3.12 DP-Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
      2. 7.4.2 DDC Functional Description
    5. 7.5 Register Maps
      1. 7.5.1  Local I2C Control BIT Access TAG Convention
      2. 7.5.2  BIT Access Tag Conventions
      3. 7.5.3  CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
      4. 7.5.4  CSR Bit Field Definitions, REV_ID (address = 08h )
      5. 7.5.5  CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
      6. 7.5.6  CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
      7. 7.5.7  CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
      8. 7.5.8  CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
      9. 7.5.9  CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
      10. 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
      11. 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
      12. 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
      13. 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
      14. 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
      15. 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
      16. 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
      17. 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
      18. 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
      19. 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source Side
        2. 8.2.2.2 DDC Pull Up Resistors
      3. 8.2.3 Application Curves
      4. 8.2.4 Application with DDC Snoop
        1. 8.2.4.1 Source Side HDMI Application
      5. 8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Management
      2. 8.3.2 Standby Power
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.5 Register Maps

The TDP158 local I2C interface is enabled when I2C_EN is high. The SCL_CTL and SDA_CTL terminals are used for I2C clock and data respectively. The TDP158 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to 400Kbps. The device address byte is the first byte received following the START condition from the controller device. The 7 bit device address for TDP158 decides by the combination of A0/EQ1 and A1/EQ2. Table 7-6 provides the TDP158 target address.

Table 7-6 TDP158 I2C Device Address Description
A1/A0Bit 7 (MSB)Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 (W/R)HEX
0010111100/1BC/BD
0110111010/1BA/BB
1010111000/1B8/B9
1110110110/1B6/B7

The local I2C is 5-V tolerant, and no additional circuitry required. Local I2C buses run at 400kHz supporting fast-mode I2C operation.

The following procedure is followed to write to the TDP158 I2C registers:

  1. The controller initiates a write operation by generating a start condition (S), followed by the TDP158 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TDP158 acknowledges the address cycle.
  3. The controller presents the sub-address (I2C register within TDP158) to be written, consisting of one byte of data, MSB-first.
  4. The TDP158 acknowledges the sub-address cycle.
  5. The controller presents the first byte of data to be written to the I2C register.
  6. The TDP158 acknowledges the byte transfer.
  7. The controller may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TDP158.
  8. The controller terminates the write operation by generating a stop condition (P).

The following procedure is followed to read the TDP158 I2C registers:

  1. The controller initiates a read operation by generating a start condition (S), followed by the TDP158 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  2. The TDP158 acknowledges the address cycle.
  3. The TDP158 transmit the contents of the memory registers MSB-first starting at register 00h.
  4. The TDP158 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  5. If an ACK is received, the TDP158 transmits the next byte of data.
  6. The controller terminates the read operation by generating a stop condition (P).

Note:

Upon reset, the TDP158 sub-address will always be set to 0x00. When no sub-address is included in a read operation, the TDP158 sub-address will increment from previous acknowledged read or write data byte. If it is required to read from a sub-address that is different from the TDP158 internal sub-address, a write operation with only a sub-address specified is needed before performing the read operation.

Refer to Section 7.5.1 for TDP158 local I2C register descriptions. Reads from reserved fields or addresses that are not specified return zeros. The value written to reserved fields must match the value read from the reserved field to not impact device features or performance.