ZHCSFY1F December   2016  – April 2024 TDP158

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply
    6. 5.6  Electrical Characteristics, Differential Input
    7. 5.7  Electrical Characteristics, TMDS Differential Output
    8. 5.8  Electrical Characteristics, DDC, I2C, HPD, and ARC
    9. 5.9  Electrical Characteristics, TMDS Differential Output in DP-Mode
    10. 5.10 Switching Characteristics, TMDS
    11. 5.11 Switching Characteristics, HPD
    12. 5.12 Switching Characteristics, DDC and I2C
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reset Implementation
      2. 7.3.2  Operation Timing
      3. 7.3.3  Lane Control
      4. 7.3.4  Swap
      5. 7.3.5  Main Link Inputs
      6. 7.3.6  Receiver Equalizer
      7. 7.3.7  Input Signal Detect Block
      8. 7.3.8  Transmitter Impedance Control
      9. 7.3.9  TMDS Outputs
      10. 7.3.10 Slew Rate Control
      11. 7.3.11 Pre-Emphasis
      12. 7.3.12 DP-Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
      2. 7.4.2 DDC Functional Description
    5. 7.5 Register Maps
      1. 7.5.1  Local I2C Control BIT Access TAG Convention
      2. 7.5.2  BIT Access Tag Conventions
      3. 7.5.3  CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
      4. 7.5.4  CSR Bit Field Definitions, REV_ID (address = 08h )
      5. 7.5.5  CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
      6. 7.5.6  CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
      7. 7.5.7  CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
      8. 7.5.8  CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
      9. 7.5.9  CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
      10. 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
      11. 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
      12. 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
      13. 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
      14. 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
      15. 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
      16. 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
      17. 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
      18. 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
      19. 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source Side
        2. 8.2.2.2 DDC Pull Up Resistors
      3. 8.2.3 Application Curves
      4. 8.2.4 Application with DDC Snoop
        1. 8.2.4.1 Source Side HDMI Application
      5. 8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Management
      2. 8.3.2 Standby Power
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.5.7 CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)

Figure 7-12 MISC CONTROL 0Bh Field Descriptions
76543210
SLEW_CTL_CLKReservedTERMDDC_DR_SELTMDS_CLOCK_RATIO_STATUSDDC_TRAIN_SETDISABLE
R/WRR/WR/WR/W/UR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-12 MISC CONTROL 0Bh
BitFieldTypeResetDescription
7:6SLEW_CTL_CLKR/W2’b01See Section 7.3.10
00 – Slowest ≅ 215ps
01 – Mid-Range 1 (Default) ≅ 185ps
10 – Mid-Range 2 ≅ 155ps
11 – Fastest ≅ 125ps
Values are typical
5ReservedR1’b0Reserved
4:3TERMR/W2’b10Controls termination for HDMI TX. See Section 7.3.8
00 – 150 to 300Ω
01 – No termination
10 – Follows TMDS_CLOCK_RATIO_STATUS bit (default).
When = 1 termination value is 75 to 150Ω:
When = 0 No termination
11 – 75 to 150Ω:
Note: When TMDS_CLOCK_RATIO_STATUS bit reg0Bh[1] = 1 this register will automatically be set to 11 for 75 to 150Ω but can be overwritten using this address
2DDC_DR_SELR/W1’b0Defines the DDC output speed for DDC bridge
0 – 100Kbps (default)
1 – 400Kbps
1TMDS_CLOCK_RATIO_STATUSR/W/U1’b0This field is updated from snoop of I2C write to target address 0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/SCL_SRC interface. When bit 1 of address 0xA8 offset 0x20 is written to a 1’b1 or read as a 1’b1, then this field will be set to a 1’b1. When bit 1 of address 0xA8 offset 0x20 is written to a 1’b0, then this field will be set to a 1’b0. This field is reset to default value whenever HPD_SNK is de-asserted for greater than 2 ms. The main function of this bit is to automatically set the proper TX termination when value = 1.
0 – HDMI 1.4b (default)
1 – HDMI 2.0
Note 1. When DDC_TRAIN_SETDISABLE is 1’b0 this bit will reflect the value of the DDC snoop.
Note 2. When DDC_TRAIN_SETDISABLE is 1’b1 this bit is set by I2C and DDC snoop is ignored. If this bit was set to 1 during snoop prior to the DDC_TRAIN_SETDISABLE being set to 1 it will be cleared to 0.
0DDC_TRAIN_SETDISABLER/W1’b0This field indicate the DDC training block function status.
0 – DDC training enable (default)
1 – DDC training disable –DDC snoop disabled
Note 1. When DDC_TRAIN_SETDISABLE is 1’b0 the TMDS_CLOCK_RATIO_STUATU bit will reflect the value of the DDC snoop.
Note 2. When DDC_TRAIN_SETDISABLE is 1’b1, this bit is set by I2C and DDC snoop is ignored and thus automatic TERM control is ignored and must be manually set and TMDS_CLOCK_RATIO_STATUS bit will be cleared.
Note 3. To go back to snoop and automatic TERM control this bit has to be cleared and TERM set back to automatic control.