ZHCSFY1F December 2016 – April 2024 TDP158
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Data Lane Fixed EQ Values | Clock EQ Values | DIS_HDMI 2_SWG | ||||
R | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | R | 1’b0 | Reserved |
6:3 | Data Lane Fixed EQ Values | R/W | 4’b0000 | (Section Section 7.3.6 and Table 7-3 for values) 0000 – 0dB (default) |
2:1 | Clock EQ Values | R/W | 2’b00 | 00 – 0dB (default) 01 – 1.5dB 10 – 3dB 11 – 4.5dB |
0 | DIS_HDMI 2_SWG | R/W | 1’b0 | Disables halving the clock output swing when entering HDMI 2.0 mode from TMDS_CLOCK_RATIO_STATUS. 0 – Disables TMDS_CLOCK_RATIO_STATUS control of the clock VOD so output swing is at full swing (default) 1 – Clock VOD is half of set values when TMDS_CLOCK_RATIO_STATUS states in HDMI 2.0 mode |