ZHCSGH3A March 2016 – July 2017 TAS5782M
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | RSCLK | RLRK | |||||
R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | Reserved | R/W | Reserved
|
|
1 | RSCLK | R/W | 0 | Master Mode SCLK Divider Reset – This bit, when set to 0, will reset the MCLK divider to generate SCLK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly.
0: Master mode SCLK clock divider is reset
|
0 | RLRK | R/W | 1 | Master Mode LRCLK Divider Reset – This bit, when set to 0, will reset the SCLK divider to generate LRCLK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly.
0: Master mode LRCLK clock divider is reset
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