ZHCSUW0D March   1998  – February 2024 LMC660 , LMC662

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information LMC662
    5. 5.5 Thermal Information LMC660
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Amplifier Topology
      2. 6.1.2 Compensating Input Capacitance
      3. 6.1.3 Capacitive Load Tolerance
      4. 6.1.4 Bias Current Testing
    2. 6.2 Typical Applications
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Printed Circuit Board Layout for High-Impedance Work
  8. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3.     Trademarks
    4. 7.3 静电放电警告
    5. 7.4 术语表
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

GUID-CD30933B-FDA3-4D18-BF91-4064782A917F-low.gif Figure 4-1 LMC662 D Package, 8-Pin SOIC, and P package, 8-Pin PDIP (Top View)
Table 4-1 LMC662 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
–IN A 2 Input Inverting input, channel A
+IN B 5 Input Noninverting input, channel B
–IN B 6 Input Inverting input, channel B
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
V+ 8 Power Positive (highest) power supply
V– 4 Power Negative (lowest) power supply
GUID-E4345B66-106B-4662-8A41-57CE2F2BD88F-low.gif Figure 4-2 LMC660 D Package, 14-Pin SOIC, and P package, 14-Pin PDIP (Top View)
Table 4-2 LMC660 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
+IN B 5 Input Noninverting input, channel B
+IN C 10 Input Noninverting input, channel C
+IN D 12 Input Noninverting input, channel D
–IN A 2 Input Inverting input, channel A
–IN B 6 Input Inverting input, channel B
–IN C 9 Input Inverting input, channel C
–IN D 13 Input Inverting input, channel D
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
OUT C 8 Output Output, channel C
OUT D 14 Output Output, channel D
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply