ZHCSIZ1G May   2010  – November 2018 LM98640QML-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings    
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information         
    5. 6.5 Quality Conformance Inspection
    6. 6.6 LM98640QML-SP Electrical Characteristics
    7. 6.7 AC Timing Specifications
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sampling Modes
        1. 7.3.1.1 Sample & Hold Mode
          1. 7.3.1.1.1 Sample & Hold Mode CLAMP/SAMPLE Adjust
        2. 7.3.1.2 CDS Mode
          1. 7.3.1.2.1 CDS Mode Bimodal Offset
          2. 7.3.1.2.2 CDS Mode CLAMP/SAMPLE Adjust
      2. 7.3.2 Input Bias and Clamping
        1. 7.3.2.1 Sample and Hold Mode Biasing
        2. 7.3.2.2 CDS Mode Biasing
        3. 7.3.2.3 VCLP DAC
      3. 7.3.3 Programmable Gain
        1. 7.3.3.1 CDS/SH Stage Gain
        2. 7.3.3.2 PGA Gain Plots
      4. 7.3.4 Programmable Analog Offset Correction
      5. 7.3.5 Analog to Digital Converter
      6. 7.3.6 LVDS Output
        1. 7.3.6.1 LVDS Output Voltage
        2. 7.3.6.2 LVDS Output Modes
        3. 7.3.6.3 TXFRM Output
          1. 7.3.6.3.1 Output Mode 1 - Dual Lane
          2. 7.3.6.3.2 Output Mode 2 - Quad Lane
      7. 7.3.7 Clock Receiver
      8. 7.3.8 Power Trimming
    4. 7.4 Device Functional Mode
      1. 7.4.1 Powerdown Modes
      2. 7.4.2 LVDS Test Modes
        1. 7.4.2.1 Test Mode 0 - Fixed Pattern
        2. 7.4.2.2 Test Mode 1 - Horizontal Gradient
        3. 7.4.2.3 Test Mode 2 - Vertical Gradient
        4. 7.4.2.4 Test Mode 3 - Lattice Pattern
        5. 7.4.2.5 Test Mode 4 - Stripe Pattern
        6. 7.4.2.6 Test Mode 5 - LVDS Test Pattern (Synchronous)
        7. 7.4.2.7 Test Mode 6 - LVDS Test Pattern (Asynchronous)
        8. 7.4.2.8 Pseudo Random Number Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Writing to the Serial Registers
      3. 7.5.3 Reading the Serial Registers
      4. 7.5.4 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Total Ionizing Dose
      2. 8.1.2 Single Event Latch-Up and Functional Interrupt
      3. 8.1.3 Single Event Effects
    2. 8.2 Typical Application
      1. 8.2.1 Sample/Hold Mode
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power Planes
      2. 9.1.2 Bypass Capacitors
      3. 9.1.3 Ground Plane
      4. 9.1.4 Thermal Management
  10. 10器件和文档支持
    1. 10.1 器件支持
      1. 10.1.1 开发支持
        1. 10.1.1.1 评估板
        2. 10.1.1.2 寄存器编程软件
    2. 10.2 接收文档更新通知
    3. 10.3 社区资源
    4. 10.4 出口管制提示
    5. 10.5 商标
    6. 10.6 静电放电警告
    7. 10.7 术语表
  11. 11机械、封装和可订购信息
    1. 11.1 工程样片

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • NBB|68
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.4.2 LVDS Test Modes

The LVDS test modes present programmable data patterns to the input of the LVDS serializer block. The type of pattern is selectable through the Test Pattern Control register. Once the LVDS test mode is enabled the patterns are output indefinitely. Table 4 below shows the available test pattern modes.

Table 4. Test Pattern Modes

TEST PATTERN CONTROL[6:4] TEST MODE
000 Fixed Code
001 Horizontal Gradient
010 Vertical Gradient
011 Lattice Pattern
100 Strip Pattern
101 LVDS Test Pattern (Synchronous)
110 LVDS Test Pattern (Asynchronous)
111 Reserved

Each pattern consists of a Start Period and Valid Pixel region. During the Start Period the output is the minimum code (0x0000). The Valid Pixel region contains the selected Test Pattern Mode output. The length (in pixels) of the Start period is set using the Test Pattern Start register, and the width of the Valid Pixel region is set using the Test Pattern Width register.

To start the test pattern generation, enable Test Mode using bit[1] of the Test and Scan Register (0x3D). Then load all parameters for the desired test pattern into the registers, and set Pattern Enable bit of the Test Pattern Control Register (0x34). Changing pattern parameters after the Pattern Enable bit is set may result in undesired output. The pattern will start at the next leading edge of CLPIN.