SNVS837B June   2013  – April 2016 LM3263

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  PFM Operation
      3. 7.3.3  Active Current Assist and Analog Bypass (ACB)
      4. 7.3.4  Bypass Operation
      5. 7.3.5  Dynamic Adjustment of Output Voltage
      6. 7.3.6  DC-DC Operating Mode Selection
      7. 7.3.7  Internal Synchronous Rectification
      8. 7.3.8  Current Limit
      9. 7.3.9  Timed Current Limit
      10. 7.3.10 Thermal Overload Protection
      11. 7.3.11 Start-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Low-Power Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 User States
    5. 7.5 Programming
      1. 7.5.1 RFFE Interface
      2. 7.5.2 Supported Command Sequences
      3. 7.5.3 Device Enumeration
      4. 7.5.4 GPO1
      5. 7.5.5 Trigger Registers
      6. 7.5.6 Control Interface Timing Parameters
    6. 7.6 Register Map
  8. 8 Application Information
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Recommended External Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout Considerations
    1. 10.1 Layout Guidelines
      1. 10.1.1 1. Overview
      2. 10.1.2 2. PCB
        1. 10.1.2.1 Energy Efficiency
        2. 10.1.2.2 EMI
      3. 10.1.3 3. Manufacturing Considerations
    2. 10.2 4. Layout Examples
      1. 10.2.1 DC-DC Converter
        1. 10.2.1.1 Star Connection Between VBATT, DC-DC Converter, and PA
          1. 10.2.1.1.1 VBATT Star Connection
    3. 10.3 DSBGA Package Assembly and Use
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout Considerations

10.1 Layout Guidelines

10.1.1 1. Overview

PC board layout is critical to successfully designing a DC-DC converter into a product. A properly planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final product yield.

10.1.2 2. PCB

Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC converter device, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or degraded performance of the converter.

10.1.2.1 Energy Efficiency

Minimize resistive losses by using wide traces between the power components and doubling up traces on multiple layers when possible.

10.1.2.2 EMI

By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3263, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is maintained within tolerable levels.

To help minimize radiated noise:

  • Place the LM3263 DC-DC converter, its input capacitor, and output filter inductor and capacitor close together, and make the interconnecting traces as short as possible.
  • Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3263 and the inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3263 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
  • Make the current loop area(s) as small as possible. Interleave doubled traces with ground planes or return paths, where possible, to further minimize trace inductances.
  • The Active Current Assist and Bypass (ACB) trace must be kept short and routed directly from ACB pads to the VOUT pad at the inductor.

To help minimize conducted noise in the ground-plane:

  • Reduce the amount of switching current that circulates through the ground plane — connect PGND bump of the LM3263 and its input filter capacitor together using generous component-side copper fill as a pseudo-ground plane. Then connect this copper fill to the system ground-plane (if one is used) by multiple vias located at the input filter capacitor ground terminal. The multiple vias help to minimize ground bounce at the LM3263 by giving it a low-impedance ground connection. Do not route the PGND pad directly to the RF ground plane.
  • An additional high frequency capacitor in 01005 (0402 mm) case size is also recommended between PVIN and the RF ground plane. Do not connect to PGND directly.
  • For optimum RF performance connect the output capacitor ground to the RF ground or system ground plane. Do not connect to PGND directly.

To help minimize coupling to the voltage feedback trace of the DC-DC converter:

  • Route noise sensitive traces, such as the voltage feedback path (FB), as directly as possible from the DC-DC converter FB pad to the VOUT pad of the output capacitor, but keep them away from noisy traces between the power components.

To help minimize noise coupled back into power supplies:

  • Use a star connection to route from the VBATT power input to DC-DC converter PVIN and to VBATT_PA.
  • Route traces for minimum inductance between PVIN pads and the input capacitor(s).
  • Route traces to minimize inductance between the input capacitors and the ground plane.
  • Maximize power supply trace inductance(s) to reduce coupling among function blocks.
  • Inserting a ferrite bead in line with power supply traces can offer a favorable tradeoff in terms of board area, by attenuating noise that might otherwise propagate through the supply connections, allowing the use of fewer bypass capacitors.

10.1.3 3. Manufacturing Considerations

The LM3263 device is packaged in a 16-pin (4 × 4) array of 0.24-mm solder balls, with a 0.4-mm pad pitch. A few simple design rules go a long way to ensuring a good layout.

  • Pad size must be 0.225 ± 0.02 mm. Solder mask opening must be 0.325 ± 0.02 mm.
  • As a thermal relief, connect to each pad with 9-mil wide, 6-mil long traces and incrementally increase each trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly. Refer toAN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).

10.2 4. Layout Examples

LM3263 simplified_LM3263_RF_EVM_schematic.gif Figure 30. Simplified LM3263 RF Evaluation Board Schematic
LM3263 Top_View_of_RF_Evaluation_Board_with_PAs.gif Figure 31. Top View of RF Evaluation Board With PAs

10.2.1 DC-DC Converter

LM3263 Top_Layer.gif Figure 32. Top Layer
LM3263 Board_Layer_2_FB_SVDD_PACB_PVIN.gif Figure 33. Board Layer 2 – FB, SVDD, PACB, PVIN
LM3263 Board_Layer_3_SW_ACB.gif Figure 34. Board Layer 3 – SW, ACB
LM3263 Board_Layer_4_VCC_PA_SYSTEM_GND_PLANE.gif Figure 35. Board Layer 4 – VCC_PA, System GND Plane
LM3263 Board_Layer_5_VBATT_Connection.gif Figure 36. Board Layer 5 – VBATT Connection
LM3263 Multiple_Board_Layers_VBATT_Supply_Star_Connection.gif Figure 37. Multiple Board Layers – VBATT Supply Star Connection

10.2.1.1 Star Connection Between VBATT, DC-DC Converter, and PA

10.2.1.1.1 VBATT Star Connection

It is critically important to use a star connection from VBATT supply to the LM3263 PVIN and from VBATT to PA modules as implementing a daisy-chain supply connection may add noise to the PA output.

LM3263 VBATT_Start_Connection_on_PCIN_and_VBATT_PA.gif Figure 38. VBATT Star Connection on PCIN and VBATT_PA

10.3 DSBGA Package Assembly and Use

Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow techniques, as detailed in AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board must be used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap from holding the device off the surface of the board and interfering with mounting. See SNVA009 for specific instructions how to do this.

The 16-pin package used for the LM3263 has 265 micron (nominal) solder balls and requires 0.225-mm pads for mounting the circuit board. The trace to each pad must enter the pad with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad must be about 0.142-mm wide, for a section approximately 0.127-mm long, as a thermal relief. Then each trace must neck up or down to its optimal width.

An important criterion is symmetry to insure the solder bumps on the LM3263 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1, A3, B1, and B3 because PGND, PVIN and BGND are typically connected to large copper planes; inadequate thermal relief can result in inadequate re-flow of these bumps.

The DSBGA package is optimized for the smallest possible size in applications with red-opaque or infrared-opaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges that are sensitive to light in the red and infrared range shining on the exposed die edges of the package.