7.3.1 PWM Operation

The LM3263 operates in PWM mode when forced-PWM mode operation is selected (SMPS_CFG [5] set to 0b). The switching frequency is modulated, and the switcher regulates the output voltage by changing the energy per cycle to support the load required. During the first portion of each switching cycle, the control block in the LM3263 turns on the internal PFET switch. This allows current to flow from the input through the inductor and to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (V_BATT – VSET)/L, by storing energy in its magnetic field.

During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET and to the output filter capacitor and load, which ramps the inductor current down with a slope of –VSET/L. The output filter capacitor stores charge when the inductor current is greater than the load current and releases it when the inductor current is less than the load current, smoothing the voltage across the load.

At the next rising edge of the clock, the cycle repeats. An increase of load pulls the output voltage down, increasing the error signal. As the error signal increases, the peak inductor current becomes higher therefore increasing the average inductor current. The output voltage is therefore regulated by modulating the PFET switch on time to control the average current sent to the load. The circuit generates a duty-cycle modulated rectangular signal that is averaged using a low pass filter formed by the inductor and output capacitor. The output voltage is equal to the average of the duty-cycle modulated rectangular signal.

7.3.2 PFM Operation

When auto-PFM mode operation is selected (SMPS_CFG [5] set to 1b), the LM3263 automatically transitions from PWM operation into PFM operation if the average inductor current is less than 60 mA (minimum) and the difference between V_BATT – VSET ≥ 0.6 V. The switcher regulates the fixed output voltage by transferring a fixed amount of energy during each cycle and modulating the frequency to control the total power delivered to the output. The converter switches only as needed to support the demand of the load current, therefore maximizing efficiency. If there is an increase in load current during PFM mode to more than 120 mA (typical), the part automatically transitions into PWM mode. A 20 mA (typical) hysteresis window exists between PFM and PWM transitions. After a transient event, the part temporarily operates in PWM mode to quickly charge or discharge the output. This is true for start-up conditions or if the mode operation is changed from forced-PWM to auto-PFM mode (SMPS_CFG [5] toggled from 0b to 1b). Once the output reaches its target output voltage, and the load is less than 60 mA (minimum), then the device seamlessly transitions into PFM mode (assuming the device is not in forced-bypass condition).

7.3.3 Active Current Assist and Analog Bypass (ACB)

The 3GPP time mask requirement for 2G requires high current to be sourced by the LM3263. These high currents are required for a small time during transients or under a heavy load. Overrating the switching inductor for these higher currents increases the solution size and is not an optimum solution. Thus, to allow an optimal inductor size for such a load, an alternate current path is provided from the input supply through the ACB pin. Once the switcher current limit I_{LIM,PFET,SteadyState} is reached, the ACB circuit starts providing the additional current required to support the load. The ACB circuit also minimizes the dropout voltage by having the analog bypass FET in parallel with VSET. The LM3263 can provide up to 2.5 A (minimum) of current in bypass mode.

7.3.4 Bypass Operation

The bypass circuit provides an analog bypass function with very low dropout resistance (R_{tot_drop} = 45 mΩ typical). When SMPS_CFG [4] is set to 0b, the part is in automatic bypass mode which automatically determines the amount of bypass needed to maintain voltage regulation. When the input supply voltage to the LM3263 is lowered to a level where the commanded duty cycle is higher than what the converter is capable of providing, the part goes into pulse-skipping mode. The switching frequency is reduced to maintain a low and well behaved output voltage ripple. The analog bypass circuit allows the converter to stay in regulation until full bypass is reached (100% duty cycle operation). The converter comes out of full bypass and back into analog bypass regulation mode with a similar reverse process.

To operate the device at the Forced-Bypass mode, set REGISTER_0 to 7Fh or VSET_CTRL to FEh-FFh.

7.3.5 Dynamic Adjustment of Output Voltage

The LM3263 can be dynamically programmed to an output voltage from 0.4 V to 3.6 V with 30 mV or 15 mV steps. REGISTER_0 [6:0] is set to 0Dh to 78h with 30-mV output voltage steps, and VSET_CTRL [7:0] is set to 1Bh to F0h with 15-mV steps. Although the output voltage can be programmed lower than 0.4 V and higher than 3.6 V by setting the registers, the device might suffer from larger output ripple voltage, higher current limit operation, and decreased linearity.

7.3.6 DC-DC Operating Mode Selection

Programming SMPS_CFG [5] changes the state of the converter to one of the two allowed modes of operation. SMPS_CFG [5] default is 0b, and the device operates in forced-PWM mode (PWM only). Setting the register bit to 1b sets the device for automatic transition between PFM/PWM mode operation. In this mode, the converter operates in PFM mode to maintain the output voltage regulation at very light loads and transitions into PWM mode at loads exceeding 120 mA (typical). Setting the register bit to 0b sets the device for PWM mode operation. The switching operation is in PWM mode only, and the switching frequency is also 2.7 MHz (typical). The device operates in forced-bypass mode when SMPS_CFG [4] is set to 1b.

For typical operation mode is set to auto-PFM and auto-bypass modes by setting SMPS_CFG = 20h.

Table 1 shows the LM3263 parameters for the given modes.

7.3.7 Internal Synchronous Rectification

The LM3263 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop, thus increasing efficiency. The reduced forward voltage drop in the internal NFET synchronous rectifier significantly improves efficiency for low output voltage operation. The NFET is designed to conduct through its intrinsic body diode during the transient intervals, eliminating the need of an external diode.

7.3.8 Current Limit

The LM3263 current limit feature protects the converter during current overload conditions. Both SW and ACB pins have positive and negative current limits. The positive and negative current limits bound the SW and ACB currents in both directions. The SW pin has two positive current limits. The I_{LIM,PFET,SteadyState} current limit triggers the ACB circuit. Once the peak inductor current exceeds I_{LIM,PFET,SteadyState}, the ACB circuit starts assisting the switcher and provides just enough current to keep the inductor current from exceeding I_{LIM,PFET,SteadyState} allowing the switcher to operate at maximum efficiency. Transiently a second current limit (I_{LIM,PFET,Transient}) of 1.9 A (typical, 2.1 A maximum) limits the maximum peak inductor current possible. The output voltage falls out of regulation only after both SW and ACB output pin currents reach their respective current limits of I_{LIM,PFET,Transient} and I_LIM,P-ACB.

7.3.9 Timed Current Limit

If the load or output short-circuit pulls the output voltage to 0.3 V or lower, and the peak inductor current sustains I_{LIM,PFET,SteadyState} more than 10 µs, the LM3263 switches to a timed current limit mode. In this mode, the internal PFET switch is turned off. After approximately 30 µs, the device returns to the normal operation.

7.3.10 Thermal Overload Protection

The LM3263 device has a thermal overload protection that protects itself from short-term misuse and overload conditions. If the junction temperature exceeds 150°C, the LM3263 shuts down. Normal operation resumes after the temperature drops below 125°C. Prolonged operation in thermal overload condition may damage the device and is therefore not recommended.

7.3.11 Start-Up

The waveform in Figure 19 shows the start-up sequence and sample conditions. First, VBATT (=PVIN=SVDD=PACB) must take on a value from 2.7 V to 5.5 V. After VBATT is ensured to be beyond 2.7 V, VIO can be set 1.8 V. Next, setting PM_TRIG [7:6] to 38h enables active mode. Finally, VSET can be programmed to a value that corresponds to the desired output voltage. The LM3263 output voltage then goes to the programmed VSET value. To optimize the start-up time and behavior of the output voltage, the LM3263 starts up in PWM mode even when the operating mode selected is auto-PFM mode (SMPS_CFG [5] set to 1b) if the output load current is ≤ 60 mA (minimum), the LM3263 then seamlessly transitions into PFM mode.

Figure 19. Non-Triggered Start-Up Sequence

Figure 20. Triggered Start-Up Sequence

7.4.1 Shutdown Mode

Shutdown mode is entered whenever the voltage on the VIO pin is 0 V. The communications and the controls are not powered. In this mode, the current consumption is 0.02 µA (typical).

7.4.2 Low-Power Mode

Low-power mode is the initial default state when VIO is applied. In this mode, the DC-DC is disabled, and its SW is tri-state. The current consumption is minimized 0.225 µA (typical). This mode can be entered by programming any one of three registers below:

• Register 00h REGISTER_0 [6:0] to 00h;
• Register 03h VSET_CTRL[7:0] to 00h or 01h;
• Register 1Ch PM_TRIG [7:6] to 10b.

7.4.3 Standby Mode

In standby mode, switching is stopped, and the output power FETs are placed are tri-state. The standby mode can be entered by setting PM_TRIG [7:6] and REGISTER_0 or VSET_CTRL registers.

• Register 00h REGISTER_0 [6:0] to 02h;
• Register 03h VSET_CTRL [7:0] to 04h or 05h;
• Register 1Ch PM_TRIG [7:6] to 00b.

7.4.4 Active Mode

The active mode is a DC-DC converter operating mode that allows the device to function, process RFFE commands, and respond to RFFE commands. This mode can be entered by setting register 1Ch PM_TRIG [7:6] to 00b. Once the device is the active Mode, the DC-DC converter operating mode and the output voltage can be programmed by using REGISTER_0 [6:0] and VSET_CTRL[7:0] registers.

7.4.5 User States

Specified output voltage range is 0.4 V to 3.6 V.

Writing to and reading back from REGISTER_0 and VSET_CTRL access the same internal VSET register. Writing to VSET_CTRL programs the full 8 bits VSET value. Writing to REGISTER_0 programs 7 MSB of VSET with LSB set to zero. When REGISTER_0 is written, the internal VSET register LSB bit[0] always takes a value of 0 and subsequent read of VSET_CTRL bit[0] is read back as 0.

Figure 21. LM3263 User State Diagram

7.5.1 RFFE Interface

The digital control serial bus interface provides MIPI RF front-end control Interface compatible access to the programmable functions and registers on the device. The LM3263 uses a three-pin digital interface: two for bidirectional communications between the IC’s connected to the bus, along with an interface voltage reference VIO that also acts as asynchronous enable and reset. When VIO voltage supply is applied to the bus, it enables the Slave interface and resets the user-defined Slave registers to the default settings. The LM3263 can be set to shutdown mode via the asynchronous VIO signal or low-power mode by setting the appropriate register via the serial bus interface. The two communication lines are serial data (SDATA), and clock (SCLK). SCLK and SDATA must be held low until VIO is present. The LM3263 connects as slave on a single-master serial bus interface.

The SDATA signal is bidirectional, driven by the Master or a Slave. Data is written on the rising edge (transition from logical level zero to logical level one) of the SCLK signal by both Master and Slaves. Master and Slave both read the data on the falling edge (transition from logical level one to logical level zero) of the SCLK signal. A logic-low level applied to VIO signal powers off the digital interface.

7.5.2 Supported Command Sequences

Figure 22. Register 0 Write

Figure 23. Register Write

Figure 24. Register Read

7.5.3 Device Enumeration

The interface component recognizes broadcast Slave Address (SID) of 0000b and is configured, via internal interface signals, with a unique SID address (USID) and a group SID address (GSID). The USID is set to 0100b and GSID set to 0000b. The register-set component typically sets the USID to a fixed value; however, it is also possible to select a second pre-set USID if a second LM3263 device is needed on the board. This second User ID can be set by forcing a voltage > 1.36 V at the GPO1 pin for USID = 0101b. Refer to GPO1 for detailed usage and programmability of the USID. The USID can also be re-programmed via the standard protocol for programming the RFFE as defined in the RFFE spec. The USID must not be programmed to the reserved broadcast slave id of 0000b. A value of 0000b is ignored by the device.

7.5.4 GPO1

GPO1 has two functions. The first function is an input to select the default USID, and the second function is to be a general purpose output.

The state of the GPO1 pin at start-up determines the default USID. If the GPO1 pin is low or left floating at start-up, the USID is 0100b. If the GPO1 pin is high at start-up, the USID is 0101b. One method to set the GPO1 pin high is to place a pullup resistor (39 KΩ) on the GPO1 pin.

When the GPO1 pin is used as the general purpose output, GPO_CTRL [6] must be set to 1b. Once it has been enabled as the general purpose output, GPO_CTRL [7] determines the state driven to the GPO1 pin. The pullup resistor must be placed either as an external pullup on the board or through an internal pullup on the general purpose input which is tied to the GPO1 pin.

The GPO1 pin can be left floating if unused.

7.5.5 Trigger Registers

Trigger registers are indicated in the RFFE register map by the Trigger column. All trigger registers are tied to each of the TRIG_0-2 register bits. When a trigger register is written directly across the RFFE interface, the new value is not loaded into the register until one of the TRIG0-2 register bits is written with a 1 and the associated TRIG_MSK_x bit for that TRIG_x is not set. (Triggers are ignored when their associated masking bit is set.) When all 3 TRIG_MSK_0-2 bits are set (all triggers are masked) the trigger feature is disabled, and any trigger registers are loaded directly at the time of the write operation to that register rather than waiting for a trigger event to update.

7.5.6 Control Interface Timing Parameters

Figure 25. Clock Timing

Figure 26. Setup and Hold Timing