SNOSC66D MARCH   2012  – September 2016 LM3017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 True Shutdown
      2. 7.3.2 Operation of the EN/MODE Pin
      3. 7.3.3 EN/MODE Control
      4. 7.3.4 Overvoltage Protection
      5. 7.3.5 Thermal Protection
      6. 7.3.6 Current Limit Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Boost Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Start-Up Boost Mode
      5. 7.4.5 Pass-Through Mode
      6. 7.4.6 Start-Up Pass-Through Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Programming the Output Voltage
        2. 8.2.2.2  Power Inductor Selection
        3. 8.2.2.3  Setting the Output Current
        4. 8.2.2.4  Additional Slope Compensation
        5. 8.2.2.5  Current Limit With Additional Slope Compensation
        6. 8.2.2.6  Power Diode Selection
        7. 8.2.2.7  Low-Side MOSFET Selection (Switching MOSFET)
        8. 8.2.2.8  Pass MOSFET Selection (High-Side MOSFET)
        9. 8.2.2.9  Input Capacitor Selection
        10. 8.2.2.10 Output Capacitor Selection
        11. 8.2.2.11 VCC Decoupling Capacitor
        12. 8.2.2.12 Slope Compensation Ramp
        13. 8.2.2.13 Control Loop Compensation
          1. 8.2.2.13.1 Compensation Network Components Calculations
          2. 8.2.2.13.2 Compensation Design Example
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Filter Capacitors
      2. 10.1.2 Sense Lines
      3. 10.1.3 Compact Layout
      4. 10.1.4 Ground Plane and Vias
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

Good board layout is critical for switching controllers such as the LM3017. First the ground plane area must be sufficient for thermal dissipation purposes and second, appropriate guidelines must be followed to reduce the effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current combined with the parasitic trace inductance generates unwanted voltage noise spikes. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may create electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, take care in layout to minimize the effect of this switching noise.

10.1.1 Filter Capacitors

Ceramic filter capacitors are most effective when the inductance of the current loops that they filter is minimized. Place CBYP as close as possible to the VIN and GND pins of the LM3017. Place CVCC next to the VCC and GND pins of the LM3017 (see Figure 16 for designators).

10.1.2 Sense Lines

The current sensing circuit in current mode devices can be easily effected by switching noise. This noise can cause duty cycle jitter which leads to increased spectral noise. RSEN must be connected to the ISEN pin with a separate trace made as short as possible, TI also recommends to route the trace that connects the VIN pin to the input voltage as close as possible to RSEN. Route this trace away from the inductor and the switch node (where D1, Q1, and L1 connect). For the voltage loop, keep RFBB/T close to the LM3017 and run a trace as close as possible to the positive side of CO. As with the ISEN line, the FB line must be routed away from the inductor and the switch node. These measures minimize the length of high impedance lines and reduce noise pickup.

10.1.3 Compact Layout

The most important layout rule is to keep the AC current loops as small as possible. Figure 30 shows the current flow of a boost converter. The top schematic shows a dotted line which represents the current flow during on-state and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents referred to as AC currents. They are the most critical ones because current is changing in very short time periods. The dotted line traces of the bottom schematic are the ones to make as short as possible. In a boost regulator the primary switching loop consists of the output capacitor, diode and MOSFET. Minimizing the area of this loop reduces the stray inductances and minimizes noise and possible erratic operation (see Layout Examples). The output capacitor(s) must be placed as close as possible to the diode cathode and MOSFET GND.

LM3017 30180997.gif Figure 30. Current Flow in a Boost Application

10.1.4 Ground Plane and Vias

A ground plane in the printed-circuit board is recommended as a means to connect the quiet end (input voltage ground side) of the input filter capacitor to the output filter capacitors and the PGND pin of the controller. Connect all the low power ground connections directly to the regulator AGND. Connect the AGND and PGND pins together through a copper area covering the entire underside of the device. Place several vias in this underside copper area to ground plane. If a via is required to connect the sensing resistor to the ISEN pin, then place that via in the inner side of the sensing resistor such that no current flow occurs. Place several vias from the ground side of the output capacitor(s) to ground place, that minimizes the path for AC current. The PGND and AGND pins have to be connected to the same ground very close to the IC. To avoid ground loop currents attach all the grounds of the system only at one point.

10.2 Layout Examples

LM3017 30180969.gif Figure 31. Layout Example (a) Top Layer, (b) Bottom Layer

10.3 Thermal Considerations

The majority of power dissipation and heat generation comes from FETs and diode. Selecting MOSFETs with exposed pads aids the power dissipation of these devices. Careful attention to RDS(on) at high temperature must be observed. Diode data sheets provide a typical junction-to-ambient thermal resistance RθJA, which can be used to estimate the operating die temperature of the Schottky. Multiplying the power dissipation by RθJA gives the temperature rise. The diode case size can then be selected to maintain the Schottky diode temperature below the operational maximum. Larger case sizes generally have lower RθJA and lower forward voltage drop.