SLVSD14A June 2017 – June 2020 DRV10983-Q1
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SSMConfig[1] | SSMConfig[0] | FGOLSel[1] | FGOLSel[0] | FGCycle[3] | FGCycle[2] | FGCycle[1] | FGCycle[0] |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ClkCycleAdjust | RMShift[2] | RMShift[1] | RMShift[0] | RMValue[3] | RMValue[2] | RMValue[1] | RMValue[0] |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | SSMConfig[1:0] | R/W | 00 | Spread spectrum modulation control
00: No spread spectrum 01: ±5% dithering 1:0: ±10% dithering 11: ±15% dithering |
13:12 | FGOLSel[1:0] | R/W | 00 | FG open-loop output select
00: FG outputs in both open loop and closed loop 01: FG outputs only in closed loop after approximately 280ms of delay 10: FG outputs closed loop and the first open loop 11: Reserved |
11:8 | FGCycle[3:0] | R/W | 0x0 | FG motor pole option
n: FG output is electrical speed / (n + 1) 0: FG / 1 (2 pole) 1: FG / 2 (4 pole) 2: FG / 3 (6 pole) 3: FG / 4 (8 pole) ... 15: FG / 16 (32 pole) |
7 | ClkCycleAdjust | R/W | 0 | 0: Full-cycle adjust
1: Half-cycle adjust |
6:4 | RMShift[2:0] | R/W | 000 | Number of shift bits to determine the motor phase resistance.
RPH_CT = RmValue << RmShift RPH_CT' = (bin) {RPhase / 0.009615} After calculating RPH_CT' value, split the value with shift number and significant number according the length of the RPH_CT' value. If the length of RPH_CT' is within 4 bits; RmValue[3:0] = RPH_CT'; RmShift[2:0] = 000 If the length of RPH_CT' is 5 bits; RmValue[3:0] = RPH_CT'[4:1]; RmShift[2:0] = 001 and so on. |
3:0 | RMValue[3:0] | R/W | 0x0 | Significant portion of the motor resistor, used in conjunction with RmShift[2:0] |