SLUS696C June   2006  – February 2019

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Standard Serial Communication (SDQ) Timing
    7. 6.7 OTP Programming Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Non-Volatile Memory
      2. 7.3.2 Authentication
      3. 7.3.3 Communication and Power
    4. 7.4 Device Functional Modes
      1. 7.4.1 Profile Command
      2. 7.4.2 Sleep Mode Description
    5. 7.5 Programming
      1. 7.5.1 Communicating with the bq26100 Device
      2. 7.5.2 Memory Descriptions
        1. 7.5.2.1 Non-Volatile OTP Memory
          1. 7.5.2.1.1 General Use – Memory Function Commands 0xF0 (Read) and 0x0F (Write)
          2. 7.5.2.1.2 General Use — Memory Function Commands 0xFA (Read) and 0xAF (Write)
          3. 7.5.2.1.3 Status – Memory Function Commands 0xAA (Read) and 0x55 (Write)
            1. 7.5.2.1.3.1 PAGE LOCK (offset = D431h) [reset = 0h]
              1. Table 5. PAGE LOCK Field Descriptions
        2. 7.5.2.2 Non-Volatile EEPROM Memory
          1. 7.5.2.2.1 General Use – Memory Function Commands 0xE0 (Read) and 0x0E (Write)
      3. 7.5.3 SHA-1 Description
      4. 7.5.4 Key Programming Description
    6. 7.6 Register Maps
      1. 7.6.1 Volatile Register Memory
        1. 7.6.1.1 Message and Digest Registers – Memory Function Command 0xDD (Read) and 0x22 (Write)
        2. 7.6.1.2 Control and Version Registers – Memory Function Command 0x88 (Read) and 0x77 (Write)
          1. 7.6.1.2.1 CTRL Register (address = 0001h) [reset = 1h]
            1. Table 9. Control Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7.5.3 SHA-1 Description

The SHA-1 is known as a one-way hash function, meaning there is no known mathematical method of computing the input given only the output. The specification of the SHA-1, as defined by FIPS 180-2, states that the input consists of 512 bit blocks with a total input length less than 264 bits. Inputs which do not conform to integer multiples of 512 bit blocks are padded before any block is input to the hash function. The SHA-1 algorithm outputs 160 bits, commonly referred to as the digest.

The full SHA-1 specification and algorithm can be found at http://csrc.nist.gov/publications/fips under FIPS 180. (As of April 23, 2004, the latest revision is FIPS 180-2.)

The bq26100 device generates an SHA-1 input block of 288 bits (total input = 160 bit message + 128 bit key). To complete the 512 bit block size requirement of the SHA-1, the bq26100 device pads the key and message with a 1, followed by 159 0’s, followed by the 64 bit value for 288 (000…00100100000), which conforms to the pad requirements specified by FIPS 180-2 9 (Figure 17).

bq26100 sha1_blk_lus696.gifFigure 17. SHA-1 Message Padding Format Example